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41. 发明授权

US07218139B1 Programmable integrated circuit providing efficient implementations of arithmetic functions 有权
标题翻译：提供算术功能的高效实现的可编程集成电路
公开(公告)号：US07218139B1
公开(公告)日：2007-05-15
申请号：US11151915
申请日：2005-06-14
申请人： Steven P. Young , Trevor J. Bauer
发明人： Steven P. Young , Trevor J. Bauer
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/1736 , G06F1/03 , G06F7/57
摘要： Efficient implementations of arithmetic functions in programmable ICs include carry chain multiplexers driven by dual-output programmable function generators. A function generator having two output signals is programmed to generate both an exclusive OR (XOR) function of first and second input signals and a second function. In some embodiments, the second function is simply the second input signal to the XOR function. In other embodiments, the second function is a different function optionally independent of the first and second input signals. The XOR function output drives the select terminal of a carry multiplexer, which selects between a carry in signal and one of the second input signal and the second function output signal to provide the carry out output signal. The sum or multiplier output value is provided by an XOR gate driven by the XOR function output and by the carry in signal, and can be optionally registered.
摘要翻译：可编程IC中算术功能的高效实现包括由双输出可编程功能发生器驱动的进位链多路复用器。具有两个输出信号的函数发生器被编程以产生第一和第二输入信号的异或（XOR）功能和第二功能。在一些实施例中，第二功能仅仅是到异或功能的第二输入信号。在其他实施例中，第二功能是可选地独立于第一和第二输入信号的不同功能。 XOR功能输出驱动进位多路复用器的选择端，它在进位信号和第二输入信号之一和第二功能输出信号之间进行选择，以提供进位输出信号。总和或乘法器输出值由XOR功能输出和进位输入信号驱动的异或门提供，可以任意注册。

42. 发明授权

US07205790B1 Programmable integrated circuit providing efficient implementations of wide logic functions 有权
标题翻译：可编程集成电路提供广泛逻辑功能的高效实现
公开(公告)号：US07205790B1
公开(公告)日：2007-04-17
申请号：US11152010
申请日：2005-06-14
申请人： Steven P. Young
发明人： Steven P. Young
IPC分类号： H03K19/173
CPC分类号： H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： Efficient implementations of wide logic functions (e.g., priority encoders, AND gates, OR gates) in programmable ICs include carry chain multiplexers driven by dual-output programmable function generators. A function generator having two output signals is programmed to generate first and second function output signals. The first and second functions can optionally share some or all of the input signals. The first function output signal drives the select terminal of a carry multiplexer, which selects between a carry in input signal and the second function output signal to provide the carry out output signal. The wide function result is provided by the final carry multiplexer in a chain of such carry multiplexers. In an exemplary wide AND gate, the first function is an AND function, and the second function is ground. In an exemplary wide OR gate, the first function is a NOR function, and the second function is power high VDD.
摘要翻译：可编程IC中的宽逻辑功能（例如，优先编码器，与门，或门）的有效实现包括由双输出可编程功能发生器驱动的进位链多路复用器。具有两个输出信号的函数发生器被编程以产生第一和第二功能输出信号。第一和第二功能可以可选地共享一些或全部输入信号。第一功能输出信号驱动进位多路复用器的选择端，其在输入信号的进位和第二功能输出信号之间进行选择以提供进位输出信号。广泛的功能结果由这种进位多路复用器的链中的最终进位多路复用器提供。在一个示例性的大AND门中，第一功能是AND功能，第二功能是接地的。在示例性的“或”门中，第一个功能是NOR功能，第二个功能是高电平VDD。

43. 发明授权

US07193433B1 Programmable logic block having lookup table with partial output signal driving carry multiplexer 有权
标题翻译：具有具有部分输出信号驱动进位多路复用器的查找表的可编程逻辑块
公开(公告)号：US07193433B1
公开(公告)日：2007-03-20
申请号：US11151988
申请日：2005-06-14
申请人： Steven P. Young
发明人： Steven P. Young
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/177
摘要： A programmable logic block provides to a carry chain multiplexer an output signal representing a partial output signal from a programmable lookup table (LUT), e.g., an output signal having a value that depends upon fewer than all of the data input signals of the LUT. In one embodiment, a first LUT output terminal provides a signal that depends upon fewer than all of the LUT data input signals, and the second LUT output terminal provides a signal that depends upon all of the LUT data input signals. In another embodiment, the first output signal depends upon X of the input signals and the second output signal depends upon Y of the input signals, X and Y being positive integers, X being less than Y. The first LUT output terminal drives a data input terminal, and the second LUT output terminal drives a select input terminal, of the carry chain multiplexer.
摘要翻译：可编程逻辑块向进位链多路复用器提供表示来自可编程查找表（LUT）的部分输出信号的输出信号，例如具有取决于LUT的数据输入信号少于所有数据的值的输出信号。在一个实施例中，第一LUT输出端提供取决于少于所有LUT数据输入信号的信号，并且第二LUT输出端提供取决于所有LUT数据输入信号的信号。在另一个实施例中，第一输出信号取决于输入信号的X，第二输出信号取决于输入信号的Y，X和Y是正整数，X小于Y.第一LUT输出端驱动数据输入终端，第二LUT输出端驱动进位链多路复用器的选择输入端。

44. 发明授权

US07109734B2 Characterizing circuit performance by separating device and interconnect impact on signal delay 有权
公开(公告)号：US07109734B2
公开(公告)日：2006-09-19
申请号：US10742300
申请日：2003-12-18
申请人： Xiao-Jie Yuan , Michael J. Hart , Zicheng G. Ling , Steven P. Young
发明人： Xiao-Jie Yuan , Michael J. Hart , Zicheng G. Ling , Steven P. Young
IPC分类号： G01R31/28
CPC分类号： G01R31/2882 , G01R31/318511 , G01R31/318516 , G01R31/3187
摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

45. 发明授权

US07068072B2 Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit 有权
标题翻译：具有用于耦合到堆叠式第二集成电路的接口瓦的集成电路
公开(公告)号：US07068072B2
公开(公告)日：2006-06-27
申请号：US10610207
申请日：2003-06-30
申请人： Bernard J. New , Robert O. Conn , Steven P. Young , Edel M. Young
发明人： Bernard J. New , Robert O. Conn , Steven P. Young , Edel M. Young
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H01L23/544 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2223/54473 , H01L2224/10135 , H01L2224/10165 , H01L2224/13021 , H01L2224/13099 , H01L2224/16111 , H01L2224/16147 , H01L2224/81136 , H01L2224/81141 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L2225/06513 , H01L2225/06565 , H01L2225/06593 , H01L2924/0001 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/14 , H01L2924/19041 , H03K19/1778 , H03K19/17796
摘要： A general purpose interface tile of a first integrated circuit includes a plurality of micropads. A second integrated circuit may be stacked on the first integrated circuit such that signals from the second integrated circuit are communicated through the micropads and the interface tile to other circuitry on the first integrated circuit. Similarly, signals from the first integrated circuit are communicated through the interface tile and the micropads to the second integrated circuit. In the event that the first integrated circuit is a programmable logic device having a programmable interconnect structure, the interface tile is part of and hooks into the programmable interconnect structure and provides a general purpose mechanism for coupling signals from the second integrated circuit to the programmable interconnect structure and/or for coupling signals from the programmable interconnect structure to the second integrated circuit.
摘要翻译：第一集成电路的通用接口板包括多个微型焊盘。第二集成电路可以堆叠在第一集成电路上，使得来自第二集成电路的信号通过微型接口和接口瓦片传送到第一集成电路上的其他电路。类似地，来自第一集成电路的信号通过接口瓦片和微型接头传送到第二集成电路。在第一集成电路是具有可编程互连结构的可编程逻辑器件的情况下，接口瓦片是可编程互连结构的一部分并挂接到可编程互连结构中，并且提供用于将来自第二集成电路的信号耦合到可编程互连结构和/或用于将来自可编程互连结构的信号耦合到第二集成电路。

46. 发明授权

US06933747B1 Structures and methods of testing interconnect structures in programmable logic devices 有权
标题翻译：在可编程逻辑器件中测试互连结构的结构和方法
公开(公告)号：US06933747B1
公开(公告)日：2005-08-23
申请号：US10684183
申请日：2003-10-10
申请人： Trevor J. Bauer , Steven P. Young , Ramakrishna K. Tanikella
发明人： Trevor J. Bauer , Steven P. Young , Ramakrishna K. Tanikella
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17764 , G01R31/2853 , G01R31/31723 , G01R31/318516 , H03K19/17736
摘要： Structures enabling the efficient testing of interconnect in programmable logic devices (PLDS), and methods utilizing these structures. A PLD includes a non-homogeneous array of programmable logic blocks and an array of standardized interconnect blocks, where the same interconnect block is used for different types of logic blocks. Coupled between each of the interconnect blocks and the associated logic block is a standardized test structure, allowing the same test configuration to be used for each interconnect block even though the interconnect blocks are associated with logic blocks of different types. In some embodiments, one or more types of logic blocks are not associated with standardized test structures. These logic blocks are coupled directly to their associated interconnect blocks, and are preferably of a type that can be configured to emulate the standardized test structure. Thus, by a correct application of configuration data all of the interconnect blocks display the same behavior.
摘要翻译：能够对可编程逻辑器件（PLDS）中的互连进行有效测试的结构以及利用这些结构的方法。 PLD包括可编程逻辑块的非均匀阵列和标准化互连块阵列，其中相同的互连块用于不同类型的逻辑块。在每个互连块和相关联的逻辑块之间耦合是标准化的测试结构，允许将相同的测试配置用于每个互连块，即使互连块与不同类型的逻辑块相关联。在一些实施例中，一个或多个类型的逻辑块不与标准化测试结构相关联。这些逻辑块直接耦合到它们相关联的互连块，并且优选地是可被配置为模拟标准化测试结构的类型。因此，通过配置数据的正确应用，所有互连块都显示相同的行为。

47. 发明授权

US06847228B1 Carry logic design having simplified timing modeling for a field programmable gate array 有权
标题翻译：进行逻辑设计具有简化的现场可编程门阵列的时序建模
公开(公告)号：US06847228B1
公开(公告)日：2005-01-25
申请号：US10300212
申请日：2002-11-19
申请人： Patrick J. Crotty , Tao Pi , Steven P. Young
发明人： Patrick J. Crotty , Tao Pi , Steven P. Young
IPC分类号： G06F7/507 , H03K19/173 , G06F7/50
CPC分类号： G06F7/507 , H03K19/1737
摘要： A configurable logic block (CLB) slice is provided that includes a single path for a carry input signal to propagate through the CLB slice as a carry output signal. This single path includes a multiplexer that is configured to receive the input signals (including the carry input signal) and provides an output signal that can be routed as the carry output signal. A driver circuit can be coupled to the output terminal of the multiplexer, thereby improving the drive of the single path. A separate path is provided in parallel with the first multiplexer path, thereby enabling the carry input signal to be applied to exclusive OR gates within the CLB slice, or to be provided as an intermediate carry output signal. The single path provides a relatively fast and consistent manner of routing the carry input signal through the CLB slice as the carry output signal. The first and second paths accommodate a carry initialization signal as well as an intermediate carry input signal.
摘要翻译：提供了可配置逻辑块（CLB）片，其包括用于进位输入信号作为进位输出信号传播通过CLB片的单个路径。该单路径包括被配置为接收输入信号（包括进位输入信号）并且提供可作为进位输出信号路由的输出信号的多路复用器。驱动器电路可以耦合到多路复用器的输出端，从而改善单路径的驱动。提供与第一多路复用器路径并行的单独路径，从而使携带输入信号能够施加到CLB切片内的异或门，或者被提供为中间进位输出信号。单路提供了一种相对快速和一致的方式，将进位输入信号通过CLB切片作为进位输出信号。第一和第二路径容纳进位初始化信号以及中间进位输入信号。

48. 发明授权

US06798241B1 Methods for aligning data and clock signals 有权
标题翻译：数据和时钟信号对齐的方法
公开(公告)号：US06798241B1
公开(公告)日：2004-09-28
申请号：US10376522
申请日：2003-02-27
申请人： Trevor J. Bauer , Steven P. Young , Christopher D. Ebeling , Jason R. Bergendahl , Arthur J. Behiel
发明人： Trevor J. Bauer , Steven P. Young , Christopher D. Ebeling , Jason R. Bergendahl , Arthur J. Behiel
IPC分类号： H03K19173
CPC分类号： H03K5/135 , H04L7/0337
摘要： Described are methods and circuits for aligning data and clock signals. Methods in accordance with some embodiments separate incoming data into three differently timed data signals: an early signal, an intermediate signal, and a late signal. The timing of the three data signals can be collectively moved with respect to the clock signal. In addition, the temporal spacing between the three signals can be adjusted so that the early and late signals define a window encompassing the intermediate signal. The three signals are aligned with respect to the clock edge to center the intermediate data signal on the clock edge. The early and late signals can be monitored to identify changes in the relative timing of the clock and data signals. Some embodiments automatically alter the timing of the data and/or clock signals to keep the intermediate data signal centered on the clock edge.
摘要翻译：描述了用于对准数据和时钟信号的方法和电路。根据一些实施例的方法将输入数据分成三个不同时间的数据信号：早期信号，中间信号和后期信号。三个数据信号的定时可以相对于时钟信号共同移动。此外，可以调整三个信号之间的时间间隔，使得早期和晚期信号限定包围中间信号的窗口。三个信号相对于时钟边沿对齐，以使中间数据信号在时钟边沿居中。可以监视早期和晚期信号以识别时钟和数据信号的相对定时的变化。一些实施例自动改变数据和/或时钟信号的定时，以使中间数据信号以时钟边缘为中心。

49. 发明授权

US06362650B1 Method and apparatus for incorporating a multiplier into an FPGA 有权
标题翻译：将乘法器并入到FPGA中的方法和装置
公开(公告)号：US06362650B1
公开(公告)日：2002-03-26
申请号：US09574714
申请日：2000-05-18
申请人： Bernard J. New , Steven P. Young
发明人： Bernard J. New , Steven P. Young
IPC分类号： H03K19177
CPC分类号： G06F15/7867 , G06F7/523 , G06F17/5054 , H03K19/17732 , H03K19/1776
摘要： One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBs) of the product are selectively provided to the first output data bus using bus multiplexer logic, and the least significant bits (LSBs) of the product are selectively provided to the second output data bus using bus multiplexer logic.
摘要翻译：一列或多列多功能瓦片位于FPGA阵列的CLB瓦片之间。每个多功能瓦片包括共享路由资源的多个功能元件。在一个实施例中，多功能瓦片包括可配置的双端口RAM和共享多功能瓦片的路由资源的乘法器。 RAM包括分别耦合到第一和第二输入数据总线的第一和第二输入端口，并且分别包括耦合到第一和第二输出数据总线的第一和第二输出端口。乘法器包括耦合以从第一和第二输入数据总线接收操作数的第一和第二操作数端口，并且响应于此提供产品。在一个实施例中，使用总线复用器逻辑将产品的最高有效位（MSB）选择性地提供给第一输出数据总线，并且使用总线选择性地将产品的最低有效位（LSB）提供给第二输出数据总线多路复用逻辑

50. 发明授权

US06297665B1 FPGA architecture with dual-port deep look-up table RAMS 有权
标题翻译：具有双端口深度查询表RAMS的FPGA架构
公开(公告)号：US06297665B1
公开(公告)日：2001-10-02
申请号：US09574445
申请日：2000-05-19
申请人： Trevor J. Bauer , Steven P. Young
发明人： Trevor J. Bauer , Steven P. Young
IPC分类号： H03K19177
CPC分类号： H03K19/1736 , G11C19/00 , H03K19/17736 , H03K19/1776
摘要： A configurable logic block (CLB) having a plurality of identical configurable logic element (CLE) slices is provided. Each CLE slice includes a plurality of function generators (lookup tables) that can be configured to form a random access memory (RAM). The width and depth of the RAM are selectable by controlling the routing of signals within the CLE slices. A hierarchy of wide function multiplexers (F5, F6, and F7 multiplexers) are provided to selectively route read data values from the lookup tables. Another set of multiplexers is used to selectively route write data values to the lookup tables. These multiplexers can be configured to provide a single write data value to all of the lookup tables to form a deep RAM. Alternatively, these multiplexers can be configured to provide one write data value to half of the lookup tables, and another write data value to the other half of the lookup tables. This pattern repeats down to the level where these multiplexers can be configured to provide a different write data value to each of the lookup tables. A write control circuit is also provided in each CLE slice to provide write enable signals to the lookup tables in a manner consistent with the selected RAM size. Read and write addresses are provided in a manner that enables the CLB to be operated as a dual-port RAM having selectable width and depth.
摘要翻译：提供具有多个相同可配置逻辑元件（CLE）片的可配置逻辑块（CLB）。每个CLE切片包括可被配置成形成随机存取存储器（RAM）的多个功能发生器（查找表）。通过控制CLE切片内信号的路由可以选择RAM的宽度和深度。提供了多功能多路复用器（F5，F6和F7多路复用器）的层次结构，用于选择性地从查找表路由读取数据值。另一组多路复用器用于选择性地将写入数据值路由到查找表。这些多路复用器可以被配置为向所有查找表提供单个写数据值以形成深RAM。或者，这些多路复用器可以被配置为向查找表的一半提供一个写入数据值，并将另一个写入数据值提供给查找表的另一半。该模式重复到这些复用器可被配置为向每个查找表提供不同的写入数据值的级别。在每个CLE片中还提供写入控制电路，以与所选择的RAM大小一致的方式向查找表提供写使能信号。提供读写地址，使得CLB能够作为具有可选宽度和深度的双端口RAM来操作。

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