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41. 发明申请

US20130062677A1 SELF-ALIGNED BOTTOM PLATE FOR METAL HIGH-K DIELECTRIC METAL INSULATOR METAL (MIM) EMBEDDED DYNAMIC RANDOM ACCESS MEMORY 有权
标题翻译：用于金属高K介电金属绝缘体金属（MIM）嵌入式动态随机存取存储器的自对准底板
公开(公告)号：US20130062677A1
公开(公告)日：2013-03-14
申请号：US13228767
申请日：2011-09-09
申请人： Zhengwen Li , Damon B. Farmer , Michael P. Chudzik , Keith Kwong Hon Wong , Jian Yu , Zhen Zhang , Chengwen Pei
发明人： Zhengwen Li , Damon B. Farmer , Michael P. Chudzik , Keith Kwong Hon Wong , Jian Yu , Zhen Zhang , Chengwen Pei
IPC分类号： H01L21/20 , H01L27/06
CPC分类号： H01L27/10829 , H01L21/84 , H01L27/10861 , H01L27/1203 , H01L28/91 , H01L29/945
摘要： A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.
摘要翻译：提供一种存储器件和形成存储器件的方法，其包括具有金属半导体合金的下电极的电容器。在一个实施例中，存储器件包括存在于半导体衬底中的沟槽，其包括在掩埋介电层顶部上的绝缘（SOI）半导体层，其中所述掩埋介电层位于基底半导体层的顶部。电容器存在于沟槽中，其中电容器包括金属半导体合金的下电极，其具有与基底半导体层的上表面自对准的上边缘，高k电介质节点层和上层金属电极。存储器件还包括与电容器电连通的传输晶体管。

42. 发明授权

US08354309B2 Method of providing threshold voltage adjustment through gate dielectric stack modification 有权
标题翻译：通过栅介质叠层修改提供阈值电压调整的方法
公开(公告)号：US08354309B2
公开(公告)日：2013-01-15
申请号：US13347014
申请日：2012-01-10
申请人： Brian J. Greene , Michael P. Chudzik , Shu-Jen Han , William K. Henson , Yue Liang , Edward P. Maciejewski , Myung-Hee Na , Edward J. Nowak , Xiaojun Yu
发明人： Brian J. Greene , Michael P. Chudzik , Shu-Jen Han , William K. Henson , Yue Liang , Edward P. Maciejewski , Myung-Hee Na , Edward J. Nowak , Xiaojun Yu
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/823462 , H01L21/28229 , H01L21/84 , H01L27/1203
摘要： Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.
摘要翻译：在掺杂半导体阱上形成多种类型的栅叠层。在掺杂半导体阱上形成高介电常数（高k）栅极电介质。在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。然后在阈值电压调整氧化物层上形成导电栅极材料层。一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。

43. 发明授权

US08232606B2 High-K dielectric and metal gate stack with minimal overlap with isolation region 有权
标题翻译：高K电介质和金属栅极堆叠与隔离区域重叠
公开(公告)号：US08232606B2
公开(公告)日：2012-07-31
申请号：US13150378
申请日：2011-06-01
申请人： Michael P. Chudzik , William K. Henson , Renee T. Mo , Jeffrey Sleight
发明人： Michael P. Chudzik , William K. Henson , Renee T. Mo , Jeffrey Sleight
IPC分类号： H01L29/76
CPC分类号： H01L29/517 , H01L21/28123 , H01L21/823842 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.
摘要翻译：公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。

44. 发明授权

US08105892B2 Thermal dual gate oxide device integration 有权
标题翻译：热双栅氧化器器件集成
公开(公告)号：US08105892B2
公开(公告)日：2012-01-31
申请号：US12542768
申请日：2009-08-18
申请人： Byeong Y. Kim , Michael P. Chudzik
发明人： Byeong Y. Kim , Michael P. Chudzik
IPC分类号： H01L21/8238
CPC分类号： H01L27/0922 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/517 , H01L29/7833
摘要： A method is provided that includes providing a semiconductor substrate including at least a thin gate oxide pFET device region and a thick gate oxide pFET device region and forming a thin gate oxide pFET within the thin gate oxide pFET device region and a thick gate oxide pFET within the thick gate oxide pFET device region. The thin gate oxide pFET that is formed includes a layer of SiGe on an upper surface of the thin gate oxide pFET device region, a high k gate dielectric located on an upper surface of the layer of SiGe, a pFET threshold voltage adjusting layer located on an upper surface of the high k gate dielectric, and a gate conductor material atop the pFET threshold voltage adjusting layer. The thick gate oxide pFET that is formed includes a thermal oxide located on an upper surface of the thick gate oxide pFET device region, a silicon layer located on an upper surface of the thermal oxide and a gate conductor material located atop the silicon layer.
摘要翻译：提供了一种方法，其包括提供至少包括薄栅极氧化物pFET器件区域和厚栅极氧化物pFET器件区域的半导体衬底，并在薄栅极氧化物pFET器件区域内形成薄栅极氧化物pFET，并在其内形成厚栅极氧化物pFET 厚栅氧化物pFET器件区域。所形成的薄栅氧化物pFET包括在薄栅极氧化物pFET器件区域的上表面上的SiGe层，位于SiGe层的上表面上的高k栅极电介质，pFET阈值电压调节层，位于高k栅极电介质的上表面，以及pFET阈值电压调节层顶部的栅极导体材料。形成的厚栅极氧化物pFET包括位于厚栅极氧化物pFET器件区域的上表面上的热氧化物，位于热氧化物的上表面上的硅层和位于硅层顶部的栅极导体材料。

45. 发明授权

US08021939B2 High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods 失效
标题翻译：高k介质和金属栅极堆叠与隔离区域和相关方法的重叠最小
公开(公告)号：US08021939B2
公开(公告)日：2011-09-20
申请号：US11954775
申请日：2007-12-12
申请人： Michael P. Chudzik , William K. Henson , Renee T. Mo , Jeffrey W Sleight
发明人： Michael P. Chudzik , William K. Henson , Renee T. Mo , Jeffrey W Sleight
IPC分类号： H01L21/8238
CPC分类号： H01L29/517 , H01L21/28123 , H01L21/823842 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.
摘要翻译：公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。

46. 发明申请

US20100244206A1 METHOD AND STRUCTURE FOR THRESHOLD VOLTAGE CONTROL AND DRIVE CURRENT IMPROVEMENT FOR HIGH-K METAL GATE TRANSISTORS 审中-公开
标题翻译：用于高K金属栅极晶体管的阈值电压控制和驱动电流改进的方法和结构
公开(公告)号：US20100244206A1
公开(公告)日：2010-09-30
申请号：US12414794
申请日：2009-03-31
申请人： Huiming Bu , Michael P. Chudzik , Wei He , Rashmi Jha , Young-Hee Kim , Siddarth A. Krishnan , Renee T. Mo , Naim Moumen , Wesley C. Natzle
发明人： Huiming Bu , Michael P. Chudzik , Wei He , Rashmi Jha , Young-Hee Kim , Siddarth A. Krishnan , Renee T. Mo , Naim Moumen , Wesley C. Natzle
IPC分类号： H01L23/00 , H01L21/314
CPC分类号： H01L21/28202 , H01L21/28176 , H01L21/28185 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.
摘要翻译：形成器件的方法包括提供衬底，在衬底上形成界面层，在界面层上沉积高k电介质层，在高k电介质层上沉积氧气清除层并执行退火。高k金属栅极晶体管包括衬底，衬底上的界面层，界面层上的高k电介质层和高k电介质层上的氧清除层。

47. 发明申请

US20100181630A1 DIRECT CONTACT BETWEEN HIGH-K/METAL GATE AND WIRING PROCESS FLOW 有权
标题翻译：高K /金属门与接线工艺流程之间的直接接触
公开(公告)号：US20100181630A1
公开(公告)日：2010-07-22
申请号：US12355953
申请日：2009-01-19
申请人： Huiming Bu , Michael P. Chudzik , Ricardo A. Donaton , Naim Moumen , Hongwen Yan
发明人： Huiming Bu , Michael P. Chudzik , Ricardo A. Donaton , Naim Moumen , Hongwen Yan
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/4958 , H01L21/28079 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A low resistance contact is formed to a metal gate or a transistor including a High-K gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride.
摘要翻译：通过在栅极堆叠上施加衬垫，在栅堆叠之间施加填充材料，将填充材料平坦化，将填充材料平坦化，形成低电阻接触到金属栅极或包括高集成度密度集成电路中的高K栅极电介质的晶体管支持高分辨率光刻，相互选择性地蚀刻填充材料和衬垫以形成通孔并用金属，金属合金或导电金属化合物如氮化钛填充通孔。

48. 发明申请

US20090294920A1 METHOD FOR FORMING DUAL HIGH-K METAL GATE USING PHOTORESIST MASK AND STRUCTURES THEREOF 有权
标题翻译：使用光电隔离膜形成双高金属栅的方法及其结构
公开(公告)号：US20090294920A1
公开(公告)日：2009-12-03
申请号：US12132146
申请日：2008-06-03
申请人： Michael P. Chudzik , Rashmi Jha , Naim Moumen , Keith Kwong Hon Wong , Ying H. Tsang
发明人： Michael P. Chudzik , Rashmi Jha , Naim Moumen , Keith Kwong Hon Wong , Ying H. Tsang
IPC分类号： H01L23/58 , H01L21/311
CPC分类号： H01L21/31133 , H01L21/31127 , H01L21/31138
摘要： Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N2/H2) or ammonia (NH3) may be used to remove the photoresist mask. With the use of the plasma nitrogen-hydrogen forming gas (N2/H2) or a plasma ammonia (NH3), no apparent organic residual is observed.
摘要翻译：公开了使用光致抗蚀剂掩模及其结构形成前端（FEOL）双高k栅极的方法。所公开方法的一个实施例包括在FEOL CMOS结构的衬底上沉积高k电介质膜，然后在其上沉积光致抗蚀剂; 根据光致抗蚀剂图案化高k电介质; 之后除去光致抗蚀剂。去除光致抗蚀剂包括使用有机溶剂，然后除去包括有机和/或碳膜的残留光致抗蚀剂。去除残留的光致抗蚀剂可以包括脱气工艺，或称为烘烤工艺。或者，可以使用形成氮气的气体（即，氮气和氢气的混合物）（N 2 / H 2）或氨（NH 3）以除去光致抗蚀剂掩模。通过使用等离子体形成氮气的气体（N 2 / H 2）或等离子体氨（NH 3），没有观察到明显的有机残留。

49. 发明申请

US20090280631A1 Electroless Metal Deposition For Dual Work Function 失效
标题翻译：无功金属沉积双功能功能
公开(公告)号：US20090280631A1
公开(公告)日：2009-11-12
申请号：US12117769
申请日：2008-05-09
申请人： Jeffrey P. Gambino , Michael P. Chudzik , Renee T. Mo
发明人： Jeffrey P. Gambino , Michael P. Chudzik , Renee T. Mo
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/82345 , H01L21/823462 , H01L29/4966 , H01L29/517
摘要： The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric layer atop the semiconducting surface of the substrate; forming a block mask atop the second device region of the substrate, wherein the first device region of the substrate is exposed; forming a first metal layer atop the high-k dielectric layer present in the first device region of the substrate; removing the block mask to expose a portion of the high-k dielectric layer in the first device region of the substrate; forming a second metal layer atop the portion of the high-k dielectric layer in the second device region and atop the first metal in the first device region of the substrate; and forming gate structures in the first and second device regions of the substrate.
摘要翻译：本发明在一个实施例中提供了一种形成半导体器件的方法，包括提供包括半导体表面的衬底，该衬底包括第一器件区域和第二器件区域; 在衬底的半导体表面上方形成高k电介质层; 在所述衬底的所述第二器件区域的顶部形成掩模掩模，其中所述衬底的所述第一器件区域被暴露; 在存在于所述衬底的第一器件区域中的高k电介质层的顶部形成第一金属层; 去除所述块掩模以暴露所述衬底的所述第一器件区域中的所述高k电介质层的一部分; 在所述第二器件区域中的所述高k电介质层的所述部分的顶部上形成第二金属层，并且在所述衬底的所述第一器件区域中的所述第一金属顶上形成第二金属层; 以及在所述衬底的所述第一和第二器件区域中形成栅极结构。

50. 发明授权

US07569466B2 Dual metal gate self-aligned integration 有权
标题翻译：双金属栅极自对准集成
公开(公告)号：US07569466B2
公开(公告)日：2009-08-04
申请号：US11303715
申请日：2005-12-16
申请人： Alessandro C. Callegari , Michael P. Chudzik , Bruce B. Doris , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
发明人： Alessandro C. Callegari , Michael P. Chudzik , Bruce B. Doris , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823842
摘要： A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.
摘要翻译：包括至少一个n型场效应晶体管（nFET）和至少一个p型场效应晶体管（pFET）的半导体结构，其分别包括具有nFET行为的金属栅极和pFET行为，而不包括上多晶硅栅极提供电极。本发明还提供一种制造这种半导体结构的方法。

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