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41. 发明申请

US20080087921A1 Image sensor device suitable for use with logic-embedded CIS chips and methods for making the same 有权
标题翻译：适用于逻辑嵌入式CIS芯片的图像传感器装置及其制造方法
公开(公告)号：US20080087921A1
公开(公告)日：2008-04-17
申请号：US11542064
申请日：2006-10-03
申请人： Chung-Yi Yu , Chia-Shiung Tsai , Shih-Chi Fu
发明人： Chung-Yi Yu , Chia-Shiung Tsai , Shih-Chi Fu
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L27/14627 , H01L27/14621 , H01L27/14632 , H01L27/14636 , H01L27/14685 , H01L27/14687
摘要： An image sensor device is provided. A substrate has a photosensor region formed therein and/or thereon. An interconnection structure is formed over the substrate, and includes metal lines formed in inter-metal dielectric (IMD) layers. At least one IMD-level micro-lens is/are formed in at least one of the IMD layers over the photosensor region. Preferably, barrier layers are located between the IMD layers. Preferably, each of the barrier layers at each level has a net thickness limited to 100 angstroms or less at locations over the photosensor region, except at locations where the IMD-level micro-lenses are located. The IMD-level micro-lenses and the etch stop layers preferably have a refractive index greater than that of the IMD layers. A cap layer is preferably formed on the metal lines, especially when the metal lines include copper. An upper-level micro-lens may be located on a level that is above the interconnection structure.
摘要翻译：提供图像传感器装置。衬底在其中和/或其上形成有光电传感器区域。在衬底上形成互连结构，并且包括在金属间电介质（IMD）层中形成的金属线。在光电传感器区域中的至少一个IMD层中形成至少一个IMD级微透镜。优选地，阻挡层位于IMD层之间。优选地，除了在IMD级微透镜所在的位置之外，每个级别的每个阻挡层的净厚度在光电传感器区域之外的位置处具有限制在100埃或更小的净厚度。 IMD级微透镜和蚀刻停止层优选具有大于IMD层的折射率的折射率。优选在金属线上形成覆盖层，特别是当金属线包括铜时。上级微透镜可以位于互连结构之上的层上。

42. 发明申请

US20080044984A1 METHODS OF AVOIDING WAFER BREAKAGE DURING MANUFACTURE OF BACKSIDE ILLUMINATED IMAGE SENSORS 审中-公开
标题翻译：在背光照明图像传感器制造过程中避免浪涌破裂的方法
公开(公告)号：US20080044984A1
公开(公告)日：2008-02-21
申请号：US11465047
申请日：2006-08-16
申请人： Yuan-Chih Hsieh , Chung-Yi Yu , Gwo-Yuh Shiau , Shih-Chi Fu , Ming Chyi Liu , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Chung-Yi Yu , Gwo-Yuh Shiau , Shih-Chi Fu , Ming Chyi Liu , Chia-Shiung Tsai
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/304 , H01L27/14618 , H01L27/14687 , H01L2924/0002 , H01L2924/00
摘要： A process for forming backside illuminated devices is disclosed. Specifically, the process reduces processing damage to wafers caused by poor bond quality at the wafer edge ring. In one embodiment, a wafer edge trimming step is implemented prior to bonding the wafer to the substrate. A pre-grind blade is used to create a straight edge around the wafer perimeter, eliminating any sharp edges. In another embodiment, edge trimming is performed after the wafer has been bonded to the substrate, and a pre-grind blade is used to remove portion of the wafer edge ring subject to poor bonding quality before grinding. The final thickness of the ground wafer is about 50 microns in either case.
摘要翻译：公开了一种用于形成背面照明装置的工艺。具体地说，该方法减少了由于晶片边缘环上的接合质量差而导致的对晶片的加工损坏。在一个实施例中，在将晶片接合到基板之前实现晶片边缘修剪步骤。预磨刀片用于在晶片周边周围创建直边，消除任何尖锐边缘。在另一个实施例中，在晶片已经结合到基板之后进行边缘修整，并且在研磨之前使用预研磨刀片来去除在接合质量差的条件下的部分晶片边缘环。在任一情况下，接地晶片的最终厚度为约50微米。

43. 发明授权

US07199001B2 Method of forming MIM capacitor electrodes 有权
标题翻译：形成MIM电容器电极的方法
公开(公告)号：US07199001B2
公开(公告)日：2007-04-03
申请号：US10811657
申请日：2004-03-29
申请人： Chih-Ta Wu , Kuo-Yin Lin , Tsung-Hsun Huang , Chung-Yi Yu , Lan-Lin Chao , Yeur-Luen Tu , Hsing-Lien Lin , Chia-Shiung Tsai
发明人： Chih-Ta Wu , Kuo-Yin Lin , Tsung-Hsun Huang , Chung-Yi Yu , Lan-Lin Chao , Yeur-Luen Tu , Hsing-Lien Lin , Chia-Shiung Tsai
IPC分类号： H01L21/8242
CPC分类号： H01L28/60 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.
摘要翻译：公开了一种用于在MIM（金属 - 绝缘体 - 金属）电容器的制造中形成电极的新颖方法。该方法通过在电介质层上的顶部电极沉积期间防止等离子体对电介质层的损伤，以及通过减少或防止介电层和电极或电极之间的界面层的形成来改善MIM电容器性能，在MIM电容器的制造中。该方法通常包括在衬底中图案化冠状电容器开口; 在每个冠状开口中沉积底部电极; 对底部电极进行快速热处理（RTP）或炉退火步骤; 在退火的底部电极上沉积介电层; 使用无等离子体CVD（化学气相沉积）或ALD（原子层沉积）工艺在电介质层上沉积顶部电极; 并对每个MIM电容器的顶部电极进行构图。

44. 发明授权

US09233844B2 Graded aluminum—gallium—nitride and superlattice buffer layer for III-V nitride layer on silicon substrate 有权
标题翻译：在硅衬底上用于III-V氮化物层的分级氮化镓 - 氮化镓和超晶格缓冲层
公开(公告)号：US09233844B2
公开(公告)日：2016-01-12
申请号：US13534368
申请日：2012-06-27
申请人： Chi-Ming Chen , Po-Chun Liu , Chung-Yi Yu
发明人： Chi-Ming Chen , Po-Chun Liu , Chung-Yi Yu
IPC分类号： H01L31/00 , B82Y10/00 , B82Y40/00 , H01L21/02 , H01L29/10 , H01L29/20 , H01L29/66 , H01L29/778
CPC分类号： B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/02458 , H01L21/02507 , H01L21/0251 , H01L21/0254 , H01L29/1075 , H01L29/2003 , H01L29/66462 , H01L29/7786
摘要： The present disclosure is directed to an integrated circuit and a method for the fabrication of the integrated circuit. The integrated circuit includes a lattice matching structure. The lattice matching structure can include a first buffer region, a second buffer region and a superlattice structure formed from AlxGa1-xN/AlyGa1-yN layer pairs.
摘要翻译：本公开涉及用于制造集成电路的集成电路和方法。集成电路包括晶格匹配结构。晶格匹配结构可以包括由Al x Ga 1-x N / Al y Ga 1-y N层对形成的第一缓冲区，第二缓冲区和超晶格结构。

45. 发明申请

US20130099282A1 FinFET Device And Method Of Manufacturing Same 有权
标题翻译： FinFET器件及其制造方法相同
公开(公告)号：US20130099282A1
公开(公告)日：2013-04-25
申请号：US13277669
申请日：2011-10-20
申请人： Chi-Ming Chen , Chung-Yi Yu , Ho-Yung David Hwang
发明人： Chi-Ming Chen , Chung-Yi Yu , Ho-Yung David Hwang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/8258 , H01L27/0605 , H01L27/0886 , H01L27/0924 , H01L29/66795 , H01L29/785
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first dielectric layer disposed over the substrate. The semiconductor device further includes a buffer layer disposed over the substrate and between first and second walls of a trench of the dielectric layer. The semiconductor device further includes an insulator layer disposed over the buffer layer and between the first and second wall of the trench of the dielectric layer. The semiconductor device also includes a second dielectric layer disposed over the first dielectric layer and the insulator layer. Further, the semiconductor device includes a fin structure disposed over the insulator layer and between first and second walls of a trench of the second dielectric layer.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性的半导体器件包括：衬底，包括设置在衬底上的第一介电层。该半导体器件还包括一个缓冲层，该缓冲层设置在该衬底上并且位于介电层沟槽的第一和第二壁之间。半导体器件还包括设置在缓冲层之上并位于介电层沟槽的第一和第二壁之间的绝缘体层。半导体器件还包括设置在第一介电层和绝缘体层之上的第二电介质层。此外，半导体器件包括布置在绝缘体层之上以及第二介电层的沟槽的第一和第二壁之间的翅片结构。

46. 发明申请

US20130078783A1 FORMING A PROTECTIVE FILM ON A BACK SIDE OF A SILICON WAFER IN A III-V FAMILY FABRICATION PROCESS 有权
标题翻译：在III-V家族制造工艺中形成硅片背面的保护膜
公开(公告)号：US20130078783A1
公开(公告)日：2013-03-28
申请号：US13244340
申请日：2011-09-24
申请人： Chun-Feng Nieh , Chung-Yi Yu , Hung-Ta Lin
发明人： Chun-Feng Nieh , Chung-Yi Yu , Hung-Ta Lin
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： Provided is a method of fabricating a semiconductor device. The method includes forming a first dielectric layer over a first surface and a second surface of a silicon substrate. the first and second surfaces being opposite surfaces. A first portion of the first dielectric layer covers the first surface of the substrate, and a second portion of the first dielectric layer covers the second surface of the substrate. The method includes forming openings that extend into the substrate from the first surface. The method includes filling the openings with a second dielectric layer. The method includes removing the first portion of the first dielectric layer without removing the second portion of the first dielectric layer.
摘要翻译：提供一种制造半导体器件的方法。该方法包括在硅衬底的第一表面和第二表面上形成第一电介质层。第一和第二表面是相对的表面。第一介电层的第一部分覆盖基板的第一表面，并且第一介电层的第二部分覆盖基板的第二表面。该方法包括形成从第一表面延伸到基底中的开口。该方法包括用第二介电层填充开口。该方法包括在不去除第一介电层的第二部分的情况下去除第一介电层的第一部分。

47. 发明授权

US08334187B2 Hard mask for thin film resistor manufacture 有权
标题翻译：薄膜电阻制造的硬掩模
公开(公告)号：US08334187B2
公开(公告)日：2012-12-18
申请号：US12824495
申请日：2010-06-28
申请人： Li-Wen Chang , Der-Chyang Yeh , Chung-Yi Yu , Hsun-Chung Kuang , Hua-Chou Tseng , Chih-Ping Chao , Ming Chyi Liu , Yuan-Tai Tseng
发明人： Li-Wen Chang , Der-Chyang Yeh , Chung-Yi Yu , Hsun-Chung Kuang , Hua-Chou Tseng , Chih-Ping Chao , Ming Chyi Liu , Yuan-Tai Tseng
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01L28/24
摘要： Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer.
摘要翻译：公开了制造诸如薄膜电阻器的集成电路器件的方法。一种示例性方法包括提供半导体衬底; 在所述半导体衬底上形成电阻层; 在所述电阻层上形成硬掩模层，其中所述硬掩模层包括所述电阻层上的阻挡层和所述阻挡层上的电介质层; 以及在所述硬掩模层中形成暴露所述电阻层的一部分的开口。

48. 发明申请

US20090294886A1 METHOD OF MAKING WAFER STRUCTURE FOR BACKSIDE ILLUMINATED COLOR IMAGE SENSOR 有权
标题翻译：制造背面照明彩色图像传感器的波形结构的方法
公开(公告)号：US20090294886A1
公开(公告)日：2009-12-03
申请号：US12537167
申请日：2009-08-06
申请人： Tzu-Hsuan Hsu , Chris Hsieh , Dun-Nian Yaung , Chung-Yi Yu
发明人： Tzu-Hsuan Hsu , Chris Hsieh , Dun-Nian Yaung , Chung-Yi Yu
IPC分类号： H01L31/0216
CPC分类号： H01L31/18 , H01L27/1203 , H01L27/1461 , H01L27/14621 , H01L27/14627 , H01L27/1464 , H01L27/14645 , H01L27/14685 , H01L27/14689 , H01L27/148
摘要： An integrated circuit device is provided. The integrated circuit device can include a substrate; a first radiation-sensing element disposed over a first portion of the substrate; and a second radiation-sensing element disposed over a second portion of the substrate. The first portion comprises a first radiation absorption characteristic, and the second portion comprises a second radiation absorption characteristic different from the first radiation absorption characteristic.
摘要翻译：提供集成电路装置。集成电路器件可以包括衬底; 设置在所述基板的第一部分上的第一辐射感测元件; 以及设置在所述基板的第二部分上的第二辐射感测元件。第一部分包括第一辐射吸收特性，第二部分包括与第一辐射吸收特性不同的第二辐射吸收特性。

49. 发明申请

US20090189233A1 CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译： CMOS图像传感器及其制造方法
公开(公告)号：US20090189233A1
公开(公告)日：2009-07-30
申请号：US12020149
申请日：2008-01-25
申请人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu , Chi-Hsin Lo , Feng-Jia Shiu , Chung-Yi Yu
发明人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu , Chi-Hsin Lo , Feng-Jia Shiu , Chung-Yi Yu
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： H01L27/14625 , H01L27/14627 , H01L27/14636 , H01L27/14685
摘要： An optical image sensor is fabricated by forming a pixel array and a peripheral region surrounding the pixel array on a semiconductor substrate, the peripheral region containing peripheral circuitry. An inter-level-dielectric layer is formed over the substrate and a plurality of interconnect wiring layers are formed over the inter-level-dielectric layer. Each interconnect wiring layer includes interconnecting metal features and a layer of inter-level-dielectric material covering the interconnecting metal features. The plurality of interconnect wiring layers are provided in a manner that there are N levels of wiring layers in the peripheral region and 1 to (N−1) levels of wiring layers over the pixel array. An etch-stop layer is formed over the top-most level interconnecting metal features in the peripheral region.
摘要翻译：通过在半导体衬底上形成围绕像素阵列的像素阵列和外围区域来制造光学图像传感器，该外围区域包含外围电路。层间电介质层形成在衬底之上，并且在层间电介质层之上形成多个互连布线层。每个互连布线层包括互连金属特征和覆盖互连金属特征的层间电介质材料层。多个互连布线层的设置方式是在像素阵列的周边区域中有N层布线层和布线层的1层（N-1）层。在外围区域中最顶层的互连金属特征上形成蚀刻停止层。

50. 发明授权

US08912570B2 High electron mobility transistor and method of forming the same 有权
标题翻译：高电子迁移率晶体管及其形成方法
公开(公告)号：US08912570B2
公开(公告)日：2014-12-16
申请号：US13571169
申请日：2012-08-09
申请人： Chen-Hao Chiang , Han-Chin Chiu , Po-Chun Liu , Chi-Ming Chen , Chung-Yi Yu
发明人： Chen-Hao Chiang , Han-Chin Chiu , Po-Chun Liu , Chi-Ming Chen , Chung-Yi Yu
IPC分类号： H01L29/20
CPC分类号： H01L29/7784 , H01L29/0891 , H01L29/2003 , H01L29/66462 , H01L29/7787
摘要： A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are in contact with the second III-V compound layer. A n-type doped region underlies each source feature and drain feature in the second III-V compound layer. A p-type doped region underlies each n-type doped region in the first III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the source feature and the drain feature.
摘要翻译：高电子迁移率晶体管（HEMT）包括第一III-V族化合物层。第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。源特征和漏极特征与第二III-V复合层接触。在第二III-V化合物层中的每个源特征和漏极特征的n型掺杂区域。 p型掺杂区域位于第一III-V化合物层中的每个n型掺杂区域的正下方。栅电极设置在源特征和漏极特征之间的第二III-V化合物层的一部分上。

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