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41. 发明授权

US4613381A Method for fabricating a thyristor 失效
标题翻译：制造晶闸管的方法
公开(公告)号：US4613381A
公开(公告)日：1986-09-23
申请号：US644257
申请日：1984-08-27
申请人： Tsuneo Ogura
发明人： Tsuneo Ogura
IPC分类号： H01L21/225 , H01L29/167 , H01L29/74 , H01L29/744
CPC分类号： H01L29/74 , H01L21/2252 , H01L29/167 , H01L29/744 , Y10S438/904
摘要： In a method for fabricating a thyristor in which n-type impurities are diffused in a p-base of a pnp wafer to form an n.sup.+ -emitter, the step of diffusing the n-type impurities for forming the n.sup.+ -emitter has the conditions which are set not to exceed the range where the amount of doped impurities is smaller than that which is electrically activated, thereby performing the gettering process by diffusing n-type impurities in two surfaces of the pnpn wafer in which the n.sup.+ -emitter having no defects is formed. Even if a thyristor obtained by the above processes has a high off-state voltage, it has a low on-state voltage, a short turn-off time and a small variation in a reverse recovery charge.
摘要翻译：在制造其中n型杂质扩散到pnp晶片的p基底以形成n +发射体的晶闸管的方法中，扩散用于形成n +型发射器的n型杂质的步骤具有以下条件：被设定为不超过掺杂杂质的量比电激活的量少的范围，从而通过在其中没有缺陷的n +发射体的pnpn晶片的两个表面扩散n型杂质来进行吸杂过程形成。即使通过上述处理获得的晶闸管具有高截止电压，它具有低导通状态电压，短关断时间和反向恢复电荷的小变化。

42. 发明申请

US20130082302A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20130082302A1
公开(公告)日：2013-04-04
申请号：US13612447
申请日：2012-09-12
申请人： Kazutoshi NAKAMURA , Tsuneo Ogura
发明人： Kazutoshi NAKAMURA , Tsuneo Ogura
IPC分类号： H01L29/739
CPC分类号： H01L29/41741 , H01L29/0696 , H01L29/0839 , H01L29/66348 , H01L29/7397
摘要： A semiconductor device comprises: a substrate having a first and second surface; trenches provided on the second surface; a gate electrode provided in each trench; a first-conductive-type emitter layer provided on the second surface and contacting with the trenches; and an emitter electrode provided on the second surface to extend in a longitudinal direction of the trenches, the emitter electrode having a non-contact portion partially provided in the first-conductive-type emitter layer.
摘要翻译：半导体器件包括：具有第一和第二表面的衬底; 提供在第二表面上的沟槽; 设置在每个沟槽中的栅电极; 设置在第二表面上并与沟槽接触的第一导电型发射极层; 以及设置在所述第二表面上以在所述沟槽的纵向方向上延伸的发射电极，所述发射电极具有部分地设置在所述第一导电型发射极层中的非接触部分。

43. 发明授权

US08217420B2 Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US08217420B2
公开(公告)日：2012-07-10
申请号：US12852193
申请日：2010-08-06
申请人： Tsuneo Ogura
发明人： Tsuneo Ogura
IPC分类号： H01L29/43
CPC分类号： H01L29/7397 , H01L29/0619 , H01L29/0696 , H01L29/0834 , H01L29/41708 , H01L29/7395
摘要： According to one embodiment, a power semiconductor device includes an IGBT region, first and second electrodes, and a first conductivity-type second semiconductor layer. The region functions as an IGBT element. The first electrode is formed in a surface of a second conductivity-type collector layer opposite to a first conductivity-type first semiconductor layer in the region. The second electrode is connected onto a first conductivity-type emitter layer and a second conductivity-type base layer in a surface of the first conductivity-type base layer and insulated from a gate electrode in the region. The first conductivity-type second semiconductor layer extends from the surface of the first conductivity-type base layer to the first conductivity-type first semiconductor layer around the IGBT region, and connected to the first electrode.
摘要翻译：根据一个实施例，功率半导体器件包括IGBT区域，第一和第二电极以及第一导电型第二半导体层。该区域用作IGBT元件。第一电极形成在与该区域中的第一导电型第一半导体层相反的第二导电型集电极的表面中。第二电极在第一导电型基极层的表面中连接到第一导电型发射极层和第二导电型基极层，并且与该区域中的栅电极绝缘。第一导电型第二半导体层从第一导电型基底层的表面延伸到IGBT区域周围的第一导电型第一半导体层，并与第一电极连接。

44. 发明授权

US07800168B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US07800168B2
公开(公告)日：2010-09-21
申请号：US11833401
申请日：2007-08-03
申请人： Tsuneo Ogura , Tomoki Inoue , Hideaki Ninomiya , Koichi Sugiyama
发明人： Tsuneo Ogura , Tomoki Inoue , Hideaki Ninomiya , Koichi Sugiyama
IPC分类号： H01L29/76
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/083 , H01L29/0834 , H01L29/7394 , H01L29/7397
摘要： A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.
摘要翻译：半导体器件包括第一导电类型的基底层，形成在基底层上的第一导电类型的阻挡层，从阻挡层的表面形成的沟槽到达达到阻挡层和基底层之间的界面，通过栅极绝缘膜形成在沟槽中的栅极电极，选择性地形成在阻挡层的表面部分中的第二导电类型的接触层，第一导电性的源极层形成在所述阻挡层的表面部分中以与所述沟槽中的所述接触层和所述栅极绝缘膜的侧壁接触的第一主电极以及与所述接触层和所述源极层接触的第一主电极。

45. 发明申请

US20070210350A1 POWER SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAME, AND METHOD FOR DRIVING SAME 有权
标题翻译：功率半导体器件，其制造方法及其驱动方法
公开(公告)号：US20070210350A1
公开(公告)日：2007-09-13
申请号：US11682670
申请日：2007-03-06
申请人： Ichiro Omura , Yoko Sakiyama , Hideki Nozaki , Atsushi Murakoshi , Masanobu Tsuchitani , Koichi Sugiyama , Tsuneo Ogura , Masakazu Yamaguchi , Tatsuo Naijo
发明人： Ichiro Omura , Yoko Sakiyama , Hideki Nozaki , Atsushi Murakoshi , Masanobu Tsuchitani , Koichi Sugiyama , Tsuneo Ogura , Masakazu Yamaguchi , Tatsuo Naijo
IPC分类号： H01L29/80
CPC分类号： H01L29/7397 , H01L23/4824 , H01L29/0619 , H01L29/0696 , H01L29/41775 , H01L29/4236 , H01L29/66348 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.
摘要翻译：功率半导体器件包括：半导体层，具有沿条形配置沿着第一方向延伸的沟槽; 掩埋在所述沟槽中的用于控制在所述半导体层中流动的电流的栅电极; 以及由具有比栅极电极更高的导电性的材料制成的栅极插塞，栅极插塞具有带状结构，并沿第一方向连接到栅电极。半导体层包括：第一导电类型的第一半导体层; 第二导电类型的第二半导体层，部分地设置在第一半导体层的上表面上; 第一导电类型的第三半导体层部分地设置在第二半导体层上; 以及设置在第一半导体层的下表面上的第二导电类型的第四半导体层。

46. 发明申请

US20070007537A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070007537A1
公开(公告)日：2007-01-11
申请号：US11478623
申请日：2006-07-03
申请人： Tsuneo Ogura , Ichiro Omura
发明人： Tsuneo Ogura , Ichiro Omura
IPC分类号： H01L31/0312
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0619 , H01L29/0696 , H01L29/086 , H01L29/0869 , H01L29/0878 , H01L29/1033 , H01L29/1045 , H01L29/105 , H01L29/1095 , H01L29/1608 , H01L29/41766 , H01L29/42368 , H01L29/66068 , H01L29/7397 , H01L29/7813 , H01L29/7828
摘要： A semiconductor device comprises: a first semiconductor layer of silicon carbide of a first conductivity type; a second semiconductor layer of silicon carbide of a second conductivity type selectively provided on the first semiconductor layer; a main electrode layer of silicon carbide of the first conductivity type selectively provided on the second semiconductor layer; a gate insulating film provided on the second semiconductor layer; a gate electrode formed on the gate insulating film; and a third semiconductor layer of the first conductivity type intervening a current path which is formed between the main electrode layer and the first semiconductor layer when an ON voltage is applied to the gate electrode. The third semiconductor layer is selectively provided on the first semiconductor layer and is adjacent to the second semiconductor layer. A doping density of the third semiconductor layer is higher than a doping density of the first semiconductor layer.
摘要翻译：半导体器件包括：第一导电类型的碳化硅的第一半导体层; 选择性地设置在所述第一半导体层上的第二导电类型的碳化硅的第二半导体层; 选择性地设置在第二半导体层上的第一导电类型的碳化硅主电极层; 设置在所述第二半导体层上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 以及第一导电类型的第三半导体层，当在栅电极施加导通电压时，插入形成在主电极层和第一半导体层之间的电流路径。第三半导体层选择性地设置在第一半导体层上并与第二半导体层相邻。第三半导体层的掺杂浓度高于第一半导体层的掺杂密度。

47. 发明申请

US20060145230A1 Power semiconductor switching element 有权
公开(公告)号：US20060145230A1
公开(公告)日：2006-07-06
申请号：US11293301
申请日：2005-12-05
申请人： Ichiro Omura , Wataru Saito , Tsuneo Ogura , Hiromichi Ohashi , Yoshihiko Saito , Kenichi Tokano
发明人： Ichiro Omura , Wataru Saito , Tsuneo Ogura , Hiromichi Ohashi , Yoshihiko Saito , Kenichi Tokano
IPC分类号： H01L29/94
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7397 , H01L29/7722 , H01L29/7811 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.

48. 发明授权

US4866315A Turn-on/off driving technique for insulated gate thyristor 失效
标题翻译：绝缘栅极晶闸管的开/关驱动技术
公开(公告)号：US4866315A
公开(公告)日：1989-09-12
申请号：US161095
申请日：1988-02-26
申请人： Tsuneo Ogura , Akio Nakagawa
发明人： Tsuneo Ogura , Akio Nakagawa
IPC分类号： H01L29/08 , H01L29/10 , H01L29/744 , H01L29/749 , H03K17/732
CPC分类号： H01L29/102 , H01L29/0834 , H01L29/744 , H01L29/749 , H03K17/732
摘要： A turn-on/off driving technique for an insulated gate thyristor which has a first gate electrode insulatively provided above a first base layer and functioning as a gate of MOSFET, and a second gate electrode formed on the second base layer. To drive the turn-on of the thyristor, a first voltage for rendering the MOSFET conductive is applied to the first gate electrode, while substantially simultaneously a second voltage for producing forward biasing between the second base layer and a second emitter layer is applied to the second gate electrode. To turn-off drive the thyristor, a third voltage for reverse biasing between the second emitter layer and the second base layer to stop the operation of the thyristor is applied to the second gate, while the MOSFET is kept conductive. The thyristor starts turning off in response to the voltage application. At this time, charge carriers exhausted from the second emitter layer are allowed to flow into the first base layer through the channel region of the MOSFET, thereby suppressing the local concentration of the turn-off current in the thyristor.

49. 发明授权

US09029918B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09029918B2
公开(公告)日：2015-05-12
申请号：US13232839
申请日：2011-09-14
申请人： Tsuneo Ogura
发明人： Tsuneo Ogura
IPC分类号： H01L21/02 , H01L29/417 , H01L29/10 , H01L29/66 , H01L29/739 , H01L29/78 , H01L29/06
CPC分类号： H01L29/42356 , H01L29/0696 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/66348 , H01L29/7397 , H01L29/7805 , H01L29/7813 , H01L29/7831
摘要： According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity-type base layer, a second conductivity-type base layer, a second semiconductor layer, a buried layer, a buried electrode, a gate insulating film, a gate electrode, and a second major electrode. The buried layer of the second conductivity type selectively is provided in the first conductivity-type base layer. The buried electrode is provided in a bottom portion of a trench which penetrates the second conductivity-type base layer to reach the buried layer. The buried electrode is in contact with the buried layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and is electrically connected to the second semiconductor layer and the buried electrode.
摘要翻译：根据一个实施例，半导体器件包括第一主电极，第一半导体层，第一导电型基极层，第二导电型基极层，第二半导体层，埋层，埋电极，栅极绝缘膜，栅电极和第二主电极。选择性地将第二导电类型的掩埋层设置在第一导电型基底层中。掩埋电极设置在穿过第二导电型基极层以到达掩埋层的沟槽的底部。掩埋电极与埋层接触。栅电极设置在沟槽内的栅极绝缘膜的内部。第二主电极设置在第二半导体层上并与第二半导体层和埋电极电连接。

50. 发明申请

US20130240947A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20130240947A1
公开(公告)日：2013-09-19
申请号：US13680849
申请日：2012-11-19
申请人： Tomoko Matsudai , Tsuneo Ogura
发明人： Tomoko Matsudai , Tsuneo Ogura
IPC分类号： H01L29/739 , H01L29/66
CPC分类号： H01L29/7397 , H01L27/0623 , H01L27/0629 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/0804 , H01L29/0821 , H01L29/0834 , H01L29/1004 , H01L29/407 , H01L29/417 , H01L29/41708 , H01L29/45 , H01L29/6609 , H01L29/66333 , H01L29/66348 , H01L29/7395 , H01L29/7813 , H01L29/861 , H01L29/8613
摘要： A semiconductor device formed on a substrate of a first conductivity type, including a base layer of a second conductivity disposed on a first face of the substrate, an anode layer with a higher dopant amount in a portion of the base layer, an IGBT region formed on the base layer, a diode region formed on the anode layer, a trench extending from the top of the IGBT and diode regions in to the substrate. The area occupied by the diode region is different from the area occupied by the IGBT region, but they share collector and emitter electrodes. The contact area between the diode anode layer and the emitter electrode may be adjusted by the arrangement of trenches.
摘要翻译：一种半导体器件，形成在第一导电类型的衬底上，包括设置在衬底的第一面上的第二导电性的基底层，在基底层的一部分中具有较高掺杂量的阳极层，形成的IGBT区域在基极层上，形成在阳极层上的二极管区域，从IGBT顶部延伸的沟槽和二极管区域延伸到衬底。二极管区域所占的面积与IGBT区域所占的面积不同，但共享集电极和发射极。二极管阳极层和发射电极之间的接触面积可以通过沟槽的布置进行调节。

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