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    • 44. 发明授权
    • Insulated gate semiconductor device
    • 绝缘栅半导体器件
    • US06342709B1
    • 2002-01-29
    • US09117997
    • 1998-08-11
    • Yoshitaka SugawaraKatsunori Asano
    • Yoshitaka SugawaraKatsunori Asano
    • H01L3300
    • H01L29/7811H01L29/0619H01L29/1095H01L29/1608H01L29/42368H01L29/7397H01L29/7809H01L29/7813
    • In a semiconductor device having a trench type insulated gate structure, in the case where a drift layer 2 of an n− conduction type has a high carrier density, when a high voltage is applied between a drain and a source in such a manner that a channel is not formed, the electric field strength of an insulator layer 9 below the trench type insulated gate is increased, thus causing breakdown. The withstand voltage of the semiconductor device is limited by the breakdown of the insulator layer 9, and it is difficult to realize high withstand voltage. In the characteristic of the present invention, a field relaxation semiconductor region 1 of a conduction type opposite to the conduction type of the drift layer 2 is formed within the drift layer 2 below the insulator layer 9 in the trench of the trench type insulated gate semiconductor device. Also, the thickness of a bottom portion of the insulator layer 9 provided in the trench of the trench type insulated gate semiconductor device is made significantly greater than the thickness of a lateral portion thereof.
    • 在具有沟槽型绝缘栅极结构的半导体器件中,在n型导电型漂移层2具有高载流子密度的情况下,当在漏极和源极之间施加高电压时, 通道不形成,沟槽型绝缘栅下方的绝缘体层9的电场强度增加,从而导致击穿。 半导体器件的耐电压受绝缘体层9击穿的限制,难以实现高耐压。在本发明的特征中,与导通相反的导电类型的场弛豫半导体区域1 在沟槽型绝缘栅半导体器件的沟槽中的绝缘体层9下方的漂移层2内形成漂移层2的类型。 此外,设置在沟槽型绝缘栅极半导体器件的沟槽中的绝缘体层9的底部的厚度显着大于其侧面部分的厚度。
    • 46. 发明授权
    • Solid-state switching circuit employing photon coupling suitable for
construction in form of integrated circuit
    • 采用光耦合的固态开关电路适用于集成电路形式的结构
    • US4212024A
    • 1980-07-08
    • US902498
    • 1978-05-03
    • Yoshitaka SugawaraTatsuya Kamei
    • Yoshitaka SugawaraTatsuya Kamei
    • H02H7/12H01L31/167H02M1/08H02M1/32H01L29/74
    • H01L31/167
    • A solid-state switching circuit employing photon coupling, which is controlled by a control signal, comprises a control portion which includes at least one light-emitting diode and a load current carrying portion which is formed on a di-electric isolated substrate. The load current carrying portion has a light-activated silicon controlled rectifier, the switching operation of which is controlled by photons emitted from the light-emitting diode. A transistor and a resistor are connected between the gate terminal and the cathode terminal of the light-activated silicon controlled rectifier in parallel to each other. Between the base and the emitter electrodes of the transistor, a photodiode is connected, and between the electrode connected to the n-base layer and the gate electrode of the light-activated silicon controlled rectifier, a diode is connected. And the photodiode is also activated by the photons emitted from the light-emitting diode.
    • 使用由控制信号控制的光子耦合的固态开关电路包括控制部分,该控制部分包括形成在二电隔离基板上的至少一个发光二极管和负载电流承载部分。 负载电流承载部分具有光激活的可控硅整流器,其开关操作由从发光二极管发射的光子控制。 晶体管和电阻器彼此平行地连接在光激活的可控硅整流器的栅极端子和阴极端子之间。 在晶体管的基极和发射极之间连接有光电二极管,并且连接到n基极的电极和光激活的可控硅整流器的栅电极之间连接二极管。 并且光电二极管也被从发光二极管发射的光子激活。
    • 48. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08896084B2
    • 2014-11-25
    • US13578434
    • 2011-02-23
    • Yoshitaka Sugawara
    • Yoshitaka Sugawara
    • H01L29/47H01L29/06H01L29/872H01L29/861H01L29/20H01L29/16
    • H01L29/0615H01L29/0619H01L29/0638H01L29/1602H01L29/1608H01L29/2003H01L29/8611H01L29/872
    • A semiconductor device includes a first semiconductor region of a first conductivity type and formed of a material having a band gap wider than that of silicon; a first layer selectively disposed on a surface of and forming a first junction with the first semiconductor region; a second layer selectively disposed on the first semiconductor region and forming a second junction with the first semiconductor region; a first diode formed by a region including the first junction; a second diode formed by a region including the second junction; and a fourth semiconductor region of a second conductivity type and disposed in the first semiconductor region, between and contacting the first and second junctions. A recess and elevated portion are disposed on the first semiconductor region. The first and the second junctions are formed at different depths. The second diode has a lower built-in potential than the first diode.
    • 半导体器件包括第一导电类型的第一半导体区域,并且由具有比硅的带隙宽的带隙的材料形成; 选择性地设置在与所述第一半导体区域形成第一结的表面上的第一层; 选择性地设置在所述第一半导体区域上并与所述第一半导体区域形成第二结的第二层; 由包括第一结的区域形成的第一二极管; 由包括所述第二结的区域形成的第二二极管; 以及第二导电类型的第四半导体区域,并且设置在第一半导体区域中,并且与第一和第二结点接触。 凹部和升高部分设置在第一半导体区域上。 第一和第二接头形成在不同的深度。 第二个二极管的内置电位低于第一个二极管。