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41. 发明申请

US20050173751A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20050173751A1
公开(公告)日：2005-08-11
申请号：US11002800
申请日：2004-12-03
申请人： Tomoyuki Ishii , Toshiyuki Mine , Yoshitaka Sasago , Taro Osabe
发明人： Tomoyuki Ishii , Toshiyuki Mine , Yoshitaka Sasago , Taro Osabe
IPC分类号： G11C11/34 , G11C16/04 , H01L21/8239 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/0475 , G11C16/0491 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory device that uses inversion layers formed on a surface of its semiconductor substrate as data lines, which is capable of satisfying the requirements of suppressing both characteristic variation among memory cells and bit cost. In order to achieve the above object, in the memory device, a plurality of assist gates are formed so as to be embedded in a p-type well via a silicon oxide film, respectively and silicon nanocrystal grains of about 6 nm in average diameter used for storing information are formed without being in contact with one another. Then, a plurality of word lines are formed practically in a direction vertically to the assist gates and the space between adjacent those of the plurality of word lines is set under ½ of the width (gate length) of the word lines. Consequently, the inversion layers formed at side faces of the assist gates will be used as local data lines, thereby the resistance is lowered and the writing characteristic variation among memory cells in a memory mat is suppressed.
摘要翻译：使用形成在其半导体衬底的表面上的反型层作为数据线的非易失性半导体存储器件，其能够满足抑制存储器单元之间的特性变化和位成本的要求。为了实现上述目的，在存储装置中，分别形成多个辅助栅极，以分别通过氧化硅膜嵌入p型阱中，并使用平均直径约6nm的硅纳米晶粒用于存储信息的形成而不彼此接触。然后，在垂直于辅助栅极的方向上形成多个字线，并且将多个字线的相邻字线之间的空间设置在字线的宽度（栅极长度）的1/2以下。因此，形成在辅助栅极的侧面的反转层将被用作本地数据线，从而电阻降低，并且抑制存储器垫中的存储单元之间的写入特性变化。

42. 发明申请

US20050052939A1 Semiconductor non-volatile memory 有权
标题翻译：半导体非易失性存储器
公开(公告)号：US20050052939A1
公开(公告)日：2005-03-10
申请号：US10919471
申请日：2004-08-17
申请人： Taro Osabe , Tomoyuki Ishii , Kazuo Yano , Takashi Kabayashi
发明人： Taro Osabe , Tomoyuki Ishii , Kazuo Yano , Takashi Kabayashi
IPC分类号： G11C16/04 , G11C16/10 , G11C16/26 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/02
CPC分类号： H01L27/11521 , B82Y10/00 , G11C16/0433 , G11C16/0458 , G11C16/0483 , G11C16/0491 , G11C16/10 , G11C16/26 , G11C2216/06 , H01L27/115 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.
摘要翻译：为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过细胞水平。

43. 发明申请

US20050029681A1 Semiconductor memory device and method for producing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20050029681A1
公开(公告)日：2005-02-10
申请号：US10883738
申请日：2004-07-06
申请人： Tomoyuki Ishii , Taro Osabe , Hideaki Kurata , Takeshi Sakata
发明人： Tomoyuki Ishii , Taro Osabe , Hideaki Kurata , Takeshi Sakata
IPC分类号： G11C8/00 , G11C11/56 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , B82Y10/00 , G11C11/5621 , G11C11/5671 , G11C16/0433 , G11C16/0458 , G11C16/0475 , G11C16/0491 , G11C2216/06 , H01L27/115 , H01L27/11521
摘要： Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 μm, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.
摘要翻译：公开了使用设置在半导体衬底上的反转层作为数据线的非易失性半导体存储器件。存储器件可以减少存储器单元之间的特性变化并且可以降低位成本。多个辅助栅极通过栅极氧化膜形成在p型阱的上部。在覆盖这些辅助栅极的层间绝缘体的上部形成用作控制电极的字线。这些字线的宽度例如为0.1μm，并且每个字线通过作为厚度为约20nm的氧化硅膜的侧壁间隔物与其相邻字线分开。

44. 发明授权

US06825525B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06825525B2
公开(公告)日：2004-11-30
申请号：US10338001
申请日：2003-01-08
申请人： Tomoyuki Ishii , Kazuo Yano
发明人： Tomoyuki Ishii , Kazuo Yano
IPC分类号： H01L29788
CPC分类号： G11C11/405 , G11C11/404 , H01L27/0688 , H01L27/115 , H01L27/11551 , H01L27/1156
摘要： A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.
摘要翻译：半导体存储器件包括：第一晶体管，包括源极区，漏极区，形成在绝缘膜上并连接源极区和漏极区的半导体材料的第一沟道区;以及栅电极，用于控制第一渠道区域第二晶体管，包括源极区域，漏极区域，连接源极区域和漏极区域的半导体材料的第二沟道区域，用于控制第二沟道区域的电位的第二栅电极和与第二沟道区域耦合的电荷存储区域第二通道区域通过静电容量; 其中所述第二晶体管的源极区域连接到源极线，所述第一晶体管的源极或漏极区域的一端连接到所述第二晶体管的电荷存储区域，所述源极或漏极区域的另一端的第一晶体管连接到数据线。

45. 发明授权

US06818914B2 Semiconductor element and process for manufacturing the same 失效
标题翻译：半导体元件及其制造方法
公开(公告)号：US06818914B2
公开(公告)日：2004-11-16
申请号：US09994731
申请日：2001-11-28
申请人： Tomoyuki Ishii , Kazuo Yano , Koichi Seki , Toshiyuki Mine , Takashi Kobayashi
发明人： Tomoyuki Ishii , Kazuo Yano , Koichi Seki , Toshiyuki Mine , Takashi Kobayashi
IPC分类号： H01L2906
CPC分类号： H01L29/7887 , H01L27/115 , H01L27/1203 , H01L29/685 , H01L29/7883 , Y10S438/962
摘要： A semiconductor quantum memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against noise. In order to accomplish this a control electrode is formed so as to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size. A method of forming a memory element is also disclosed including performing the following steps of forming a first insulating layer, a second insulating layer, a first conductive layer and a layer of amorphous silicon. The amorphous silicon layer is crystallized to a polycrystalline silicon film. Semiconductor drains are deposited to form charge trapping and storage regions. A fourth insulating layer is deposited over the drains and a second conductive layer is deposited over a layer of silicon dioxide to form a control electrode of the memory element.
摘要翻译：公开了一种半导体量子存储器元件，其可以容易地在多个存储元件之间共享端子，并且可以通过高电流并且抵抗噪声。为了实现这一点，形成控制电极以覆盖连接低电阻区域的整个薄膜区域。因此，该元件可以具有小尺寸并且可以高密度地存储信息。因此，可以以减小的尺寸实现高度集成的低功耗非易失性存储器件。还公开了一种形成存储元件的方法，包括执行以下步骤：形成第一绝缘层，第二绝缘层，第一导电层和非晶硅层。非晶硅层结晶成多晶硅膜。沉积半导体漏极以形成电荷捕获和存储区域。在漏极上沉积第四绝缘层，并且在二氧化硅层上沉积第二导电层以形成存储元件的控制电极。

46. 发明授权

US06787841B2 Semiconductor element and semiconductor memory device using the same 失效
标题翻译：半导体元件和使用其的半导体存储器件
公开(公告)号：US06787841B2
公开(公告)日：2004-09-07
申请号：US10650732
申请日：2003-08-29
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L2976
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.
摘要翻译：一种场效应半导体元件，其具有较少数量的元件和减小的面积，并能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。

47. 发明授权

US06787835B2 Semiconductor memories 失效
标题翻译：半导体存储器
公开(公告)号：US06787835B2
公开(公告)日：2004-09-07
申请号：US10167754
申请日：2002-06-11
申请人： Bryan Atwood , Kazuo Yano , Tomoyuki Ishii , Taro Osabe , Kazumasa Yanagisawa , Takeshi Sakata
发明人： Bryan Atwood , Kazuo Yano , Tomoyuki Ishii , Taro Osabe , Kazumasa Yanagisawa , Takeshi Sakata
IPC分类号： H01L27108
CPC分类号： H01L27/105 , G11C11/405 , G11C11/406 , G11C11/4076 , G11C2207/2281 , G11C2207/229 , H01L27/0207 , H01L27/108 , H01L27/1203
摘要： A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two- and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.
摘要翻译：本发明提供了高集成度的动态随机存取存储器。此外，提供了一种写入方法，使得减少了双晶体管和三晶体管增益单元存储器的单元尺寸。一种结合了作为写入元件的薄沟道晶体管的动态存储器，使得在本发明的存储器件中实现长的数据存储保持。通过本发明也实现了具有低操作功率和高密度的动态存储单元。

48. 发明授权

US06555882B2 Semiconductor element and semiconductor memory device using the same 失效
公开(公告)号：US06555882B2
公开(公告)日：2003-04-29
申请号：US09943444
申请日：2001-08-31
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L2976
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

49. 发明授权

US06486938B1 Line exposure type image forming apparatus 失效
标题翻译：线曝光型图像形成装置
公开(公告)号：US06486938B1
公开(公告)日：2002-11-26
申请号：US09704277
申请日：2000-11-01
申请人： Akio Morita , Tomoyuki Ishii
发明人： Akio Morita , Tomoyuki Ishii
IPC分类号： G02B2608
CPC分类号： H04N1/19589 , B41J2/471 , G02B26/0841 , H04N1/195
摘要： A line exposure type image forming apparatus having a micromirror device 40 with numerous micromirrors 41 tiltable for reflecting light incident from a light source to a predetermined exposure position on a photosensitive material 2, and a sub-scan moving mechanism 8a for moving the photosensitive material relative to the exposure position. The micromirror device is disposed such that an imaginary line linking imaging positions on the photosensitive material of the micromirrors in a predetermined line is at an angle to a direction of relative movement of the photosensitive material. As a result, an exposure dot line is produced on the photosensitive material in a main scanning direction perpendicular to the direction of relative movement by a main scanning mirror set formed of micromirrors selected in a direction at an angle to a direction of the columns of the micromirror device.
摘要翻译：具有微反射镜装置40的线曝光型图像形成装置，具有可以将从光源入射的光反射到感光材料2上的预定曝光位置的多个微反射镜41，以及用于使感光材料相对移动的副扫描移动机构8a 到曝光位置。微镜器件被布置成使得在预定线上的将微镜的感光材料上的成像位置连接的虚拟线与感光材料的相对移动方向成一角度。结果，在与感光材料的垂直于相对移动方向的主扫描方向上的感光材料上，通过主扫描反射镜组产生曝光点线，所述主扫描反射镜组是由在与微镜装置。

50. 发明授权

US06473333B1 Storage circuit with layered structure element 失效
标题翻译：具有分层结构元件的存储电路
公开(公告)号：US06473333B1
公开(公告)日：2002-10-29
申请号：US09986946
申请日：2001-11-13
申请人： Suguru Tachibana , Katsuro Sasaki , Kiyoo Itoh , Tomoyuki Ishii
发明人： Suguru Tachibana , Katsuro Sasaki , Kiyoo Itoh , Tomoyuki Ishii
IPC分类号： G11C1140
CPC分类号： G11C11/22 , G11C11/412 , G11C14/00 , Y10S257/903
摘要： The present invention provides a circuit, in which a device typified by a PLED element is built into a flip-flop. In this case, a storage node of the device is low leakage. According to the present invention, it is possible to realize a SRAM that has nonvolatility while achieving high-speed operation. It is also possible to realize a flip-flop having the same characteristics. An example of a typical mode of the present invention is a storage circuit characterized by the following: a storage element is a device incorporating: a first path for a carrier; a first mode for storing a charge that generates an electric field where conductivity of the first path is changed; and a barrier structure through which a second carrier moves in response to given voltage so that the second carrier is stored in the first node; and the storage circuit includes a second node, to which information stored in the first node is outputted steadily in a state in which power is supplied. The flip-flop and the SRAM are realized using such a basic circuit.
摘要翻译：本发明提供了一种电路，其中以触发器构建由PLED元件代表的器件。在这种情况下，设备的存储节点是低泄漏。根据本发明，可以实现具有非易失性的SRAM，同时实现高速操作。也可以实现具有相同特性的触发器。本发明的典型模式的一个例子是存储电路，其特征在于：存储元件是包括：用于载体的第一路径的装置; 用于存储产生第一路径的导电性改变的电场的电荷的第一模式; 以及阻挡结构，第二载体通过该阻挡结构响应于给定的电压移动，使得第二载体被存储在第一节点中; 并且存储电路包括第二节点，第一节点中存储的信息在供电的状态下稳定地输出。使用这样的基本电路来实现触发器和SRAM。

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