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41. 发明授权

US4588905A Digital waveform conditioning circuit 失效
标题翻译：数字波形调理电路
公开(公告)号：US4588905A
公开(公告)日：1986-05-13
申请号：US699233
申请日：1985-02-08
申请人： Tadashi Kojima
发明人： Tadashi Kojima
IPC分类号： H03M5/04 , G11B5/09 , G11B20/10 , H03K5/08 , H04L1/20 , H04L25/03 , H03K5/13 , H03K5/153 , H03K12/00
CPC分类号： H03K5/084 , H04L1/20
摘要： A digital waveform conditioning circuit for restoring a deformed digital signal into its original rectangular waveform, comprising an input terminal supplied with the deformed digital signal, a circuit for generating a reference signal by combining positive and negative voltage components rectified from positive and negative cycles of the deformed signal, a comparator for comparing the deformed signal with the reference signal, a circuit for holding an output signal of the comparator for a period controlled by a clock signal for synchronizing the output signal with the original rectangular signal, and an output terminal for receiving the output of the holding circuit.
摘要翻译：一种用于将变形的数字信号恢复成其原始矩形波形的数字波形调节电路，包括提供有变形的数字信号的输入端子，用于通过组合由正和负周期整流的正和负电压分量来产生参考信号的电路变形信号，用于将变形信号与参考信号进行比较的比较器，用于保持比较器的输出信号的电路，用于由用于使输出信号与原始矩形信号同步的时钟信号控制的周期，以及用于接收的输出端子保持电路的输出。

42. 发明授权

US4583211A Frequency detecting circuit for digital information reproducing system 失效
标题翻译：数字信息再现系统的频率检测电路
公开(公告)号：US4583211A
公开(公告)日：1986-04-15
申请号：US478641
申请日：1983-03-24
申请人： Meisei Nishikawa , Yukio Nakamura , Tadashi Kojima
发明人： Meisei Nishikawa , Yukio Nakamura , Tadashi Kojima
IPC分类号： G11B5/09 , G11B7/005 , G11B19/28 , G11B20/10 , G11B20/14 , G11B20/18 , G11B27/10 , G11B27/34 , G06M3/00 , G11B17/00 , G11B19/24
CPC分类号： G11B27/34 , G11B19/28 , G11B20/10527 , G11B20/1423 , G11B20/1806 , G11B27/10 , G11B7/005 , G11B2220/20
摘要： A circuit is disclosed which is applied for a digital audio disk (DAD) system for detecting a maximum inverting period of a digital audio signal optically read out from the DAD. The audio signal is prestored in the DAD so as to have the maximum and minimum inverting periods specially set by an eight to fourteen modulation (EFM). The detection circuit includes an edge detector for detecting pulse edges of the digital audio signal, a counter for counting pulse edge intervals on the basis of a modulating clock signal, a counter type register, and a comparator. When the register contents of the counter type register is smaller than the count value of the counter, the comparator produces a pulse signal by which said register updates the contents of the register by "1". Repeating this operation, a maximum inverting period value of the digital audio signal is obtained in a fixed period of time.
摘要翻译：公开了一种应用于数字音频盘（DAD）系统的电路，用于检测从DAD光学读出的数字音频信号的最大反相周期。音频信号预先存储在DAD中，以便具有由八到十四调制（EFM）特别设置的最大和最小反相周期。检测电路包括用于检测数字音频信号的脉冲边缘的边缘检测器，用于基于调制时钟信号计数脉冲边缘间隔的计数器，计数器类型寄存器和比较器。当计数器类型寄存器的寄存器内容小于计数器的计数值时，比较器产生脉冲信号，通过该脉冲信号将寄存器的内容更新为“1”。重复该操作，在固定的时间段内获得数字音频信号的最大反相周期值。

43. 发明授权

US4580100A Phase locked loop clock recovery circuit for data reproducing apparatus 失效
标题翻译：用于数据再现装置的锁相环时钟恢复电路
公开(公告)号：US4580100A
公开(公告)日：1986-04-01
申请号：US563259
申请日：1983-12-19
申请人： Hiroshi Suzuki , Tadashi Kojima , Mitsuru Nagata
发明人： Hiroshi Suzuki , Tadashi Kojima , Mitsuru Nagata
IPC分类号： G11B20/14 , H03L7/089 , H03K9/00 , H03L7/08
CPC分类号： G11B20/1403 , H03L7/0891
摘要： A data reproduction circuit, which can be used for reproducing audio data from an optical disc, includes a phase-locked loop which has a circuit for detecting polarity inversions of the input signal, a circuit for comparing the phases of a polarity inversion signal with a reference signal, and circuitry for generating an output clock signal which is phase-locked with the input signal, that clock being used to strobe the input signal to remove fluctuation and jitter from the input signal.
摘要翻译：可以用于从光盘再现音频数据的数据再现电路包括：锁相环，其具有用于检测输入信号的极性反转的电路，用于将极性反转信号的相位与参考信号和用于产生与输入信号锁相的输出时钟信号的电路，该时钟用于选通输入信号以从输入信号中去除波动和抖动。

44. 发明授权

US4577155A Data extracting circuit 失效
标题翻译：数据提取电路
公开(公告)号：US4577155A
公开(公告)日：1986-03-18
申请号：US532514
申请日：1983-09-15
申请人： Akira Kobayashi , Tadashi Kojima
发明人： Akira Kobayashi , Tadashi Kojima
IPC分类号： H03M5/04 , G11B20/10 , G11B20/14 , H04L25/04 , H03K5/08 , H03K5/153
CPC分类号： G11B20/10527 , G11B20/10 , G11B20/10009
摘要： A data extracting circuit for converting an analog signal derived from a D.C. component-free modulated digital signal stored on a recording medium, into a D.C. component-free digital signal with a comparator for comparing the analog signal with a reference signal to provide a compared signal. A phase inverter receives the compared signal and provides a first signal component which is in-phase with the compared signal, and a second signal component which is phase-inverted with respect to the compared signal. A clipping circuit limits the amplitude level of the first and second signal components to a predetermined level and provides first and second limited signal components. An integrating circuit separately integrates the first and second limited signal components and provides first and second integrated signals. An error amplifying circuit determines the difference between the first and second integrated signals and provides a signal corresponding to this difference to the comparator as the reference signal. The D.C. component-free digital output signal is derived from the first signal component.
摘要翻译：一种数据提取电路，用于将存储在记录介质上的无分量无调制数字信号得到的模拟信号转换为无分量数字信号，比较器用于将模拟信号与参考信号进行比较，以提供比较信号。 A相逆变器接收比较信号并提供与比较信号同相的第一信号分量和相对于比较信号相位反转的第二信号分量。削波电路将第一和第二信号分量的振幅电平限制到预定电平，并提供第一和第二有限信号分量。积分电路分别对第一和第二限制信号分量进行积分并提供第一和第二积分信号。误差放大电路确定第一和第二积分信号之间的差异，并将与该差异相对应的信号作为参考信号提供给比较器。没有直流分量的数字输出信号是从第一个信号分量导出的。

45. 发明授权

US4575835A Motor control circuit of data reproduction apparatus 失效
标题翻译：数据再现装置的电机控制电路
公开(公告)号：US4575835A
公开(公告)日：1986-03-11
申请号：US473768
申请日：1983-03-10
申请人： Meisei Nishikawa , Tadashi Kojima
发明人： Meisei Nishikawa , Tadashi Kojima
IPC分类号： H02P5/00 , G11B19/24 , G11B19/28 , G11B17/00
CPC分类号： G11B19/24
摘要： The invention relates to a motor control circuit of a data reproduction apparatus, which drives a disk motor to reproduce a data signal recorded together with a sync signal on a recording medium so as to control the disk motor in accordance with a reproduced sync signal. The frequency and phase components of the reproduced sync signal are detected, and first and second motor control signals are produced in accordance with frequency and phase detection signals, respectively. A control circuit detects whether or not the frequency detection signal falls within a predetermined range. If it is determined that the frequency detection signal does not fall within the predetermined range, the second motor control signal is kept at a predetermined value.
摘要翻译：本发明涉及一种数据再现装置的电动机控制电路，其驱动磁盘电动机以再现与记录介质上的同步信号一起记录的数据信号，以便根据再现的同步信号来控制磁盘电动机。检测再现的同步信号的频率和相位分量，并且分别根据频率和相位检测信号产生第一和第二电动机控制信号。控制电路检测频率检测信号是否在预定范围内。如果确定频率检测信号不在预定范围内，则将第二电动机控制信号保持在预定值。

46. 发明授权

US4433415A PCM Signal processor 失效
标题翻译： PCM信号处理器
公开(公告)号：US4433415A
公开(公告)日：1984-02-21
申请号：US300737
申请日：1981-09-10
申请人： Tadashi Kojima
发明人： Tadashi Kojima
IPC分类号： H03M13/00 , G11B20/18 , H03M13/27 , G06F11/10
CPC分类号： G11B20/1809
摘要： A pulse code modulation signal processor extracts data words from a serial data stream. The signal processor includes a serial-to-parallel converter to convert the data stream into parallel data words, a de-interleave circuit to add different delays, and thus synchronize with each other, the extracted data words, a circuit for forming an error pointer from the data words, an error pointer comprising data word error pointers each indicating the presence of an error in a different data word, an error pointer shift register for synchronizing the error pointer with the data words from the de-interleave means, and an error detector and corrector.
摘要翻译：脉冲编码调制信号处理器从串行数据流中提取数据字。信号处理器包括串行到并行转换器以将数据流转换为并行数据字，去交织电路以增加不同的延迟，并因此彼此同步所提取的数据字，用于形成错误指针的电路来自数据字的错误指针，包括指示不同数据字中存在错误的数据字错误指针，用于使错误指针与来自解交织装置的数据字同步的错误指针移位寄存器，以及错误指针检测器和校正器。

47. 发明授权

US4404602A PCM Signal recording system 失效
标题翻译： PCM信号记录系统
公开(公告)号：US4404602A
公开(公告)日：1983-09-13
申请号：US322278
申请日：1981-11-17
申请人： Susumu Hoshimi , Tadashi Kojima
发明人： Susumu Hoshimi , Tadashi Kojima
IPC分类号： H03M7/00 , G11B5/86 , G11B20/10 , G11B20/14 , G11B20/18 , G11B27/032 , G11B27/02 , G11B5/00
CPC分类号： G11B5/86 , G11B27/032 , G11B2220/90 , G11B2220/913
摘要： A PCM (pulse code modulation) signal recording system including a first signal processor for processing a recording signal into a predetermined PCM signal, a second signal processor for processing a reproduced PCM signal into a recording signal, a first clock signal generator generating a master clock signal, a second clock signal generator generating at least one recording clock signal from the master clock signal, the recording clock signal is supplied to the first signal processor, a third clock signal generator generating at least one reproducing clock signal from the master clock signal, the reproducing clock signal is supplied to the second signal processor, a comparator digitally comparing the phases of the second and third clock signals and producing a control signal, and a controller receiving the control signal and controlling the second or third clock signal so that they are synchronized.
摘要翻译：一种PCM（脉冲编码调制）信号记录系统，包括用于将记录信号处理成预定PCM信号的第一信号处理器，用于将再现的PCM信号处理成记录信号的第二信号处理器，产生主时钟的第一时钟信号发生器信号，第二时钟信号发生器，从主时钟信号产生至少一个记录时钟信号，记录时钟信号被提供给第一信号处理器，第三时钟信号发生器，从主时钟信号产生至少一个再现时钟信号，再现时钟信号被提供给第二信号处理器，数字比较第二和第三时钟信号的相位并产生控制信号的比较器，以及接收控制信号并控制第二或第三时钟信号的控制器，使得它们是同步

48. 发明授权

US4320510A Error data correcting system 失效
标题翻译：错误数据校正系统
公开(公告)号：US4320510A
公开(公告)日：1982-03-16
申请号：US116555
申请日：1980-01-29
申请人： Tadashi Kojima
发明人： Tadashi Kojima
IPC分类号： G11B20/18
CPC分类号： G11B20/1813
摘要： An input data signal, in which n data words W.sub.1 to W.sub.n and two check words P and Q are treated as one data block, is processed by P and Q decoding circuits. The decoded data S.sub.1 and T.sup.i-(n+1) S.sub.2 from the decoding circuits are added to each other in an adder to generate S.sub.1 +T.sup.i(n+1) S.sub.2 which is in turn selected by a gate circuit in accordance with a selection signal. The selection signal is supplied from an M matrix generator (MG) embodied as a linear feedback shift register for H(x)=X.sup.m +X.sup.g +1. The initial value of the linear feedback shift register is set in accordance with the error word data derived from an error word control circuit and the order of the data to be decoded. The decoded data sequentially selected from the gate circuit are added by an adder to be the data W.sub.je to be decoded, while at the same time those are added to the S.sub.1 by an adder to be the data W.sub.ie to be decoded. The data W.sub.je and W.sub.ie is added to the corresponding data words W.sub.i and W.sub.j of the input data signal having passed through a one-block delay circuit by an adder, whereby the error data are corrected.
摘要翻译：其中n个数据字W1至Wn和两个检查词P和Q被视为一个数据块的输入数据信号由P和Q解码电路处理。来自解码电路的解码数据S1和Ti-（n + 1）S2在加法器中彼此相加以产生S1 + Ti（n + 1）S2，S1 + Ti（n + 1）S2依次由选择电路选择信号。选择信号从实施为H（x）= Xm + Xg + 1的线性反馈移位寄存器的M矩阵发生器（MG）提供。线性反馈移位寄存器的初始值根据从误差字控制电路得到的误差字数据和要解码的数据的顺序来设定。从栅极电路顺序选择的解码数据由加法器相加，成为要解码的数据Wje，同时通过加法器将这些数据加到S1上，作为要解码的数据Wie。通过加法器将数据Wje和Wie加到已经通过一个块延迟电路的输入数据信号的相应的数据字Wi和Wj中，从而校正错误数据。

49. 发明授权

US4264863A Pulse swallow type programmable frequency dividing circuit 失效
标题翻译：脉冲吞咽式可编程分频电路
公开(公告)号：US4264863A
公开(公告)日：1981-04-28
申请号：US958341
申请日：1978-11-03
申请人： Tadashi Kojima
发明人： Tadashi Kojima
IPC分类号： H03L7/18 , H03K23/64 , H03K23/66 , H03L7/193 , H03L7/197 , H04B1/26 , H03K23/26 , H03K21/36
CPC分类号： H03L7/193 , H03K23/662 , H03K23/667
摘要： A pulse swallow type programmable frequency dividing circuit is provided which comprises a prescaler for dividing the frequency of an input signal in the frequency division ratio of 1/K or 1/(K+1) according to the contents of a control signal supplied to a control terminal; a programmable frequency divider for dividing the frequency of an output signal from the prescaler in a preset frequency division ratio; and a control signal generating circuit producing a control signal to the control terminal of the prescaler in response to an output pulse from the programmable frequency-divider, thereby changing the frequency division ratio of the prescaler. A preset number of control pulses whose pulse width is equal to a period of an output pulse signal from the prescaler are supplied from the control signal generating circuit to the control terminal of the prescaler to set the frequency division ratio of the prescaler at 1/(K+1).
摘要翻译：提供了一种脉冲吞咽型可编程分频电路，其包括：预分频器，用于根据提供给a的控制信号的内容，以1 / K或1 /（K + 1）的分频比分频输入信号的频率控制终端; 一个可编程分频器，用于以预设的分频比分频来自预分频器的输出信号的频率; 以及控制信号发生电路，响应于来自可编程分频器的输出脉冲，向预分频器的控制端产生控制信号，从而改变预分频器的分频比。其脉冲宽度等于来自预分频器的输出脉冲信号的周期的预设数量的控制脉冲从控制信号发生电路提供给预分频器的控制端，以将预分频器的分频比设置为1 /（ K + 1）。

50. 发明授权

US4178403A Mask blank and mask 失效
标题翻译：面具空白和面具
公开(公告)号：US4178403A
公开(公告)日：1979-12-11
申请号：US821777
申请日：1977-08-04
申请人： Kunio Sakurai , Tadashi Kojima , Hiroshi Itoh
发明人： Kunio Sakurai , Tadashi Kojima , Hiroshi Itoh
IPC分类号： G03F1/00 , B32B15/04
CPC分类号： G03F1/50 , G03F1/48 , Y10T428/24926 , Y10T428/26
摘要： The mask blank is provided with a transparent coating layer interposed between a transparent substrate and a mask metal layer. The transparent coating layer is made of material which is resistant to an etching solution.
摘要翻译：掩模坯料设置有介于透明基板和掩模金属层之间的透明涂层。透明涂层由耐蚀刻溶液的材料制成。

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