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41. 发明授权

US06977845B2 Semiconductor memory device and electric device with the same 有权
公开(公告)号：US06977845B2
公开(公告)日：2005-12-20
申请号：US10856986
申请日：2004-06-01
申请人： Koichi Kawai , Tomoharu Tanaka , Noboru Shibata
发明人： Koichi Kawai , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/26 , G11C16/34 , H01L27/00
CPC分类号： G11C16/3468
摘要： A semiconductor memory device includes: a plurality of cell array blocks in each of which a plurality of memory cells are arranged; address decode circuits for selecting memory cells in the cell array blocks; sense amplifier circuits for reading cell data of the cell array blocks; and a busy signal generation circuit for generating a busy signal to the chip external, wherein in a first read cycle selecting a first area in a first cell array block, cell data read operations for the first area of the first cell array block and a second area of a second cell array block are simultaneously executed, while the busy signal generation circuit generates a true busy signal, and then a read data output operation is executed for outputting the read out data of the first area held in the sense amplifier circuits to the chip external, and in a second read cycle selecting the second area in the second cell array block, after the busy signal generation circuit has output a dummy busy signal shorter in time length than the true busy signal without executing cell data read operation, a read data output operation is executed for outputting the read out data of the second area held in the sense amplifier circuits to the chip external.

42. 发明授权

US06925004B2 Semiconductor memory device for storing multivalued data 有权
公开(公告)号：US06925004B2
公开(公告)日：2005-08-02
申请号：US10689868
申请日：2003-10-20
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/10 , G11C11/56 , G11C16/04 , G11C16/12
CPC分类号： G11C16/3459 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/12 , G11C2211/5642 , G11C2211/5648
摘要： In the operation of writing the second page, the control circuit precharges the bit line in verifying data “2” in the memory cell when the DDC has data “1” in it after the data cache is set and does not precharge the bit line when the DDC has data “0” in it. As a result, when data “2” has been written into the memory cell, the bit line is at the intermediate potential, which raises the threshold voltage of the memory cell a little.

43. 发明授权

US06600676B2 Nonvolatile semiconductor memory device with a ROM block settable in the write or erase inhibit mode 有权
标题翻译：具有可设置在写或擦除禁止模式的ROM块的非易失性半导体存储器件
公开(公告)号：US06600676B2
公开(公告)日：2003-07-29
申请号：US09957019
申请日：2001-09-21
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C1622
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has a plurality of memory elements selected by an address signal. The second storage area has a plurality of memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区具有通过地址信号选择的多个存储元件。第二存储区具有通过控制信号选择的多个存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

44. 发明授权

US06373746B1 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells 有权
标题翻译：具有连接到存储单元的位线的多个数据存储部分的非易失性半导体存储器
公开(公告)号：US06373746B1
公开(公告)日：2002-04-16
申请号：US09667610
申请日：2000-09-22
申请人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
发明人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C1604
CPC分类号： G11C16/3418 , G11C7/1051 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/24 , G11C16/3431 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643 , G11C2211/5649 , G11C2211/565 , G11C2216/14
摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.
摘要翻译：具有三个以上值的数据以非易失性方式存储在存储单元中。数据电路具有多个存储电路。多个存储电路中的一个是锁存电路。多个存储电路中的另一个是电容器。锁存电路和电容器用于临时存储具有两位或更多位的程序/读数据。如果由于泄漏引起的数据变化导致程序，则使用锁存电路来刷新由电容器保持的数据。结果，即使使用多级数据，数据电路也不会变大。

45. 发明授权

US06331945B1 Non-volatile semiconductor memory capable of storing one-bit data or multi-bit data 有权
标题翻译：能够存储一位数据或多位数据的非易失性半导体存储器
公开(公告)号：US06331945B1
公开(公告)日：2001-12-18
申请号：US09528112
申请日：2000-03-17
申请人： Noboru Shibata , Tomoharu Tanaka , Hiroto Nakai , Toshio Yamamura , Susumu Fujimura
发明人： Noboru Shibata , Tomoharu Tanaka , Hiroto Nakai , Toshio Yamamura , Susumu Fujimura
IPC分类号： G11C1606
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C2211/5641 , G11C2211/5642
摘要： Data latch circuits are provided corresponding to select memory cells from or into which read or program is executed. The data latch circuits are grouped by two into sets. When 2-bit data is read from or programmed into the select memory cells, one data latch circuit is selected by a select signal, and, when 1-bit data is read or programmed, the two data latch circuits in one set are selected by a select signal. Between one or two selected data latch circuits and a data input/output buffer, data is exchanged. By so doing, changeover between 2-level data and multi-level (4-level or more-level) data concerning program or read of data into or out the memory cells becomes possible.
摘要翻译：数据锁存电路是从执行读取或程序的选择存储器单元提供的。数据锁存电路分为两组。当2位数据从选择存储单元读取或编程到选择存储单元中时，通过选择信号选择一个数据锁存电路，当读取或编程1位数据时，一组中的两个数据锁存电路由选择信号。在一个或两个选择的数据锁存电路和数据输入/输出缓冲器之间，交换数据。通过这样做，有可能在二级数据与有关程序的多级（4级或更多级）数据之间切换或将数据读入或取出存储单元变成可能。

46. 发明授权

US09129688B2 Semiconductor memory device capable of reducing chip size 有权
标题翻译：能够减少芯片尺寸的半导体存储器件
公开(公告)号：US09129688B2
公开(公告)日：2015-09-08
申请号：US13608713
申请日：2012-09-10
申请人： Katsuaki Isobe , Noboru Shibata , Toshiki Hisada
发明人： Katsuaki Isobe , Noboru Shibata , Toshiki Hisada
IPC分类号： G11C16/16 , G11C16/04 , H01L27/115
CPC分类号： G11C16/16 , G11C5/025 , G11C16/0483 , G11C16/14 , G11C16/26 , H01L23/528 , H01L27/11519 , H01L27/11524 , H01L27/1157 , H01L29/1095
摘要： According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
摘要翻译：根据一个实施例，形成在衬底中的第一导电类型的第一阱。第二导电类型的第二阱形成在第一阱中。多个存储单元，多个第一位线选择晶体管和多个第二位线选择晶体管形成在第二阱中，并且多个第一位线选择晶体管和多个第二位线选择晶体管是布置在所述读出放大器的相对于所述多个位线的多个存储单元的一侧。

47. 发明授权

US08971130B2 Semiconductor memory device capable of shortening erase time 有权
标题翻译：能够缩短擦除时间的半导体存储器件
公开(公告)号：US08971130B2
公开(公告)日：2015-03-03
申请号：US13660044
申请日：2012-10-25
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C11/34 , G11C16/14
CPC分类号： G11C16/3445 , G11C16/10 , G11C16/14 , G11C16/26
摘要： In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≦n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
摘要翻译：在存储单元阵列中，连接到多个字线和多个位线的多个存储单元被布置成矩阵。控制电路控制所述多个字线和所述多个位线的电位。在擦除操作中，控制电路使用第一擦除电压同时擦除所述多个存储单元的n个存储单元（n为等于或大于2的自然数），执行使用第一验证电平，找到超过第一验证电平的单元数k（k＆nlE; n），根据数k确定第二擦除电压，并使用第二擦除电压再次执行擦除操作。

48. 发明授权

US08634557B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08634557B2
公开(公告)日：2014-01-21
申请号：US13524271
申请日：2012-06-15
申请人： Yuji Nagai , Toshihiro Suzuki , Noboru Shibata , Taku Kato , Tatsuyuki Matsushita
发明人： Yuji Nagai , Toshihiro Suzuki , Noboru Shibata , Taku Kato , Tatsuyuki Matsushita
IPC分类号： H04K1/00
CPC分类号： H04L9/0816 , G11B20/00086 , G11B20/00115 , G11B20/0021 , G11B2220/2516 , G11B2220/60 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： According to one embodiment, a device includes a storage and an authenticator. The storage includes a first area, a second area and a third area. The first area stores NKey and SecretID, the second area stores index information. E-SecretID is generated by SecretID. The third area stores FKB including information generated by FKey. The authenticator authenticates the external device. HKey is generated by an AES encryption calculating using NKey and HC. A SKey is generated by an AES encryption process using HKey and RN. A one-way conversion calculating is performed. E-SecretID, FKB and Oneway-ID are output to the external device. The index information is read from the second area.
摘要翻译：根据一个实施例，一种设备包括存储器和认证器。存储器包括第一区域，第二区域和第三区域。第一个区域存储NKey和SecretID，第二个区域存储索引信息。 E-SecretID由SecretID生成。第三个区域存储FKB，包括FKey生成的信息。验证器验证外部设备。 HKey由使用NKey和HC的AES加密计算产生。通过使用HKey和RN的AES加密过程生成SKey。执行单向转换计算。 E-SecretID，FKB和Oneway-ID被输出到外部设备。从第二区域读取索引信息。

49. 发明授权

US08593880B2 Semiconductor memory system including a plurality of semiconductor memory devices 有权
标题翻译：半导体存储器系统包括多个半导体存储器件
公开(公告)号：US08593880B2
公开(公告)日：2013-11-26
申请号：US13598099
申请日：2012-08-29
申请人： Noboru Shibata , Hiroshi Sukegawa
发明人： Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3459
摘要： A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
摘要翻译：通信线路连接到第一和第二芯片，并保持在第一信号电平。监视电路将通信线路的信号电平从第一信号改变到第二信号电平，而第一和第二芯片中的一个使用大于参考电流的电流。当通信线路的信号电平为第二信号电平时，第一和第二芯片中的另一个被控制到等待状态，该等待状态不转移到使用大于参考电流的电流的操作状态。

50. 发明授权

US08559236B2 Nonvolatile semiconductor memory device which performs improved erase operation 有权
公开(公告)号：US08559236B2
公开(公告)日：2013-10-15
申请号：US13052158
申请日：2011-03-21
申请人： Jun Nakai , Noboru Shibata
发明人： Jun Nakai , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/14 , G11C16/26 , G11C16/344 , G11C16/3445
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.

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