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41. 发明申请

US20220254882A1 Nanosheet Devices With Hybrid Structures And Methods Of Fabricating The Same 有权
公开(公告)号：US20220254882A1
公开(公告)日：2022-08-11
申请号：US17520385
申请日：2021-11-05
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Cheng Chiang , Shi Ning Ju , Guan-Lin Chen , Jung-Chien Cheng , Chih-Hao Wang , Kuan-Lun Cheng
IPC分类号： H01L29/06 , H01L29/423 , H01L29/786 , H01L29/66 , H01L21/8234
摘要： A semiconductor structure includes a first stack of active channel layers and a second stack of active channel layers disposed over a semiconductor substrate, where the second stacking include a dummy channel layer and the first stack is free of any dummy channel layer, a gate structure engaged with the first stack and the second stack, and first S/D features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, where the second S/D features overlap with the dummy channel layer.

42. 发明申请

US20220254776A1 Hybrid Semiconductor Device 有权
公开(公告)号：US20220254776A1
公开(公告)日：2022-08-11
申请号：US17226851
申请日：2021-04-09
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jung-Chien Cheng , Kuo-Cheng Chiang , Shi Ning Ju , Guan-Lin Chen , Chih-Hao Wang , Kuan-Lun Cheng
IPC分类号： H01L27/088 , H01L29/423 , H01L29/06 , H01L29/66 , H01L29/786 , H01L21/8234
摘要： Semiconductor devices and method of forming the same are provided. In one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes two first source/drain features and a first number of nanostructures that are stacked vertically one over another and extend lengthwise between the two first source/drain features. The second transistor includes two second source/drain features and a second number of nanostructures that are stacked vertically one over another and extend lengthwise between the two second source/drain features.

43. 发明申请

US20220216203A1 GAP-INSULATED SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20220216203A1
公开(公告)日：2022-07-07
申请号：US17142640
申请日：2021-01-06
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jung-Chien Cheng , Shi Ning Ju , Guan-Lin Chen , Kuo-Cheng Chiang , Chih-Hao Wang , Kuan-Lun Cheng
IPC分类号： H01L27/092 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786 , H01L21/8238
摘要： Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a first base portion and a second base portion, an isolation feature sandwiched between the first base portion and the second base portion, a center dielectric fin over the isolation feature, a first anti-punch-through (APT) feature over the first base portion, a second APT feature over the second base portion, a first stack of channel members over the first APT feature, and a second stack of channel members over the second APT feature. The center dielectric fin is sandwiched between the first stack of channel members and the second stack of channel members as well as between the first APT feature and the second APT feature.

44. 发明申请

US20220139914A1 Semiconductor Device with Gate Isolation Structure and Method for Forming the Same 有权
公开(公告)号：US20220139914A1
公开(公告)日：2022-05-05
申请号：US17364500
申请日：2021-06-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jung-Chien Cheng , Kuo-Cheng Chiang , Shi Ning Ju , Guan-Lin Chen , Chih-Hao Wang , Kuan-Lun Cheng
IPC分类号： H01L27/092 , H01L21/8234 , H01L29/78 , H01L29/66 , H01L29/06
摘要： Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes providing a workpiece including a substrate, an isolation feature over the substrate, a first fin-shaped structure protruding through the isolation feature, and a second fin-shaped structure protruding through the isolation feature, forming a dielectric fin between the first and second fin-shaped structures, and forming first and second gate structures over the first and second fin-shaped structures, respectively. The exemplary manufacturing method also includes etching the isolation feature from the backside of the workpiece to from a trench exposing the dielectric fin, etching the dielectric fin from the backside of the workpiece to form an extended trench, and depositing a seal layer over the extended trench. The seal layer caps an air gap between the first and second gate structures.

45. 发明授权

US10910375B2 Semiconductor device and method of fabrication thereof 有权
公开(公告)号：US10910375B2
公开(公告)日：2021-02-02
申请号：US16147027
申请日：2018-09-28
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Kuo-Cheng Ching , Shi Ning Ju , Ching-Wei Tsai , Kuan-Lun Cheng , Chih-Hao Wang
IPC分类号： H01L27/092 , H01L29/66 , H01L29/78 , H01L29/49 , H01L29/51 , H01L21/308 , H01L21/8238 , H01L21/28
摘要： Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a first transistor formed in a first region of the semiconductor device. The first transistor includes a first channel structure extending between a source terminal and a drain terminal of the first transistor. The first transistor includes a second channel structure that is stacked on the first channel structure in a vertical direction above a substrate of the semiconductor device. Further, the first transistor includes a first gate structure configured to wrap around the first channel structure and the second channel structure with a first metal cap between the first channel structure and the second channel structure. The first metal cap has a different work function from another portion of the first gate structure.

46. 发明申请

US20200152632A1 Hybrid Scheme for Improved Performance for P-type and N-type FinFETs 审中-公开
公开(公告)号：US20200152632A1
公开(公告)日：2020-05-14
申请号：US16740911
申请日：2020-01-13
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Cheng Chiang , Shi Ning Ju , Ching-Wei Tsai , Kuan-Lun Cheng , Chih-Hao Wang
IPC分类号： H01L27/092 , H01L29/66 , H01L29/06 , H01L21/8238 , H01L21/762 , H01L21/311 , H01L21/306 , H01L21/02 , H01L27/12 , H01L21/84 , H01L21/308
摘要： A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.

47. 发明授权

US10535656B2 Hybrid scheme for improved performance for P-type and N-type FinFETs 有权
公开(公告)号：US10535656B2
公开(公告)日：2020-01-14
申请号：US16205443
申请日：2018-11-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Cheng Chiang , Shi Ning Ju , Ching-Wei Tsai , Kuan-Lun Cheng , Chih-Hao Wang
IPC分类号： H01L27/092 , H01L21/308 , H01L27/12 , H01L21/84 , H01L21/762 , H01L21/02 , H01L21/306 , H01L21/311 , H01L21/8238 , H01L29/06 , H01L29/66 , H01L29/04 , H01L29/165 , H01L29/78
摘要： A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.

48. 发明申请

US20170278970A1 FinFET With a Semiconductor Strip as a Base 有权
公开(公告)号：US20170278970A1
公开(公告)日：2017-09-28
申请号：US15203866
申请日：2016-07-07
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Cheng Ching , Shi Ning Ju , Ching-Wei Tsai , Chih-Hao Wang , Ying-Keung Leung , Carlos H. Diaz
IPC分类号： H01L29/78 , H01L29/161 , H01L29/66 , H01L29/24 , H01L29/267 , H01L29/06 , H01L29/08 , H01L29/165
CPC分类号： H01L29/66545 , H01L29/0653 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A method includes forming a first hard mask over a semiconductor substrate, etching the semiconductor substrate to form recesses, with a semiconductor strip located between two neighboring ones of the recesses, forming a second hard mask on sidewalls of the semiconductor strip, performing a first anisotropic etch on the second hard mask to remove horizontal portions of the second hard mask, and performing a second anisotropic etch on the semiconductor substrate using the first hard mask and vertical portions of the second hard mask as an etching mask to extend the recesses down. The method further includes removing the vertical portions of the second hard mask, and forming isolation regions in the recesses. The isolation regions are recessed, and a portion of the semiconductor strip between the isolation regions protrudes higher than the isolation regions to form a semiconductor fin.

49. 发明申请

US20160190242A1 Fin Recess Last Process for FinFet Fabrication 审中-公开
标题翻译： Fin Finite制造的Fin Recess最后流程
公开(公告)号：US20160190242A1
公开(公告)日：2016-06-30
申请号：US15063224
申请日：2016-03-07
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Cheng Ching , Shi Ning Ju , Guan-Lin Chen
IPC分类号： H01L29/06 , H01L29/10 , H01L29/423 , H01L29/161 , H01L29/78 , H01L27/088
CPC分类号： H01L29/0649 , H01L27/0886 , H01L29/105 , H01L29/161 , H01L29/42364 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A method includes forming isolation regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a hard mask strip over the isolation regions and a semiconductor strip, wherein the semiconductor strip is between two neighboring ones of the isolation regions. A dummy gate strip is formed over the hard mask strip, wherein a lengthwise direction of the dummy gate strip is perpendicular to a lengthwise direction of the semiconductor strip, and wherein a portion of the dummy gate strip is aligned to a portion of the semiconductor strip. The method further includes removing the dummy gate strip, removing the hard mask strip, and recessing first portions of the isolation regions that are overlapped by the removed hard mask strip. A portion of the semiconductor strip between and contacting the removed first portions of the isolation regions forms a semiconductor fin.
摘要翻译：一种方法包括形成从半导体衬底的顶表面延伸到半导体衬底中的隔离区，以及在隔离区和半导体条上形成硬掩模条，其中半导体条位于两个隔离区之间。在硬掩模条上形成伪栅极条，其中伪栅极条的长度方向垂直于半导体条的长度方向，并且其中伪栅极条的一部分与半导体条的一部分对准。该方法还包括去除伪栅极条，去除硬掩模条，以及凹陷由去除的硬掩模条重叠的隔离区的第一部分。半导体条带之间的部分和隔离区域的去除的第一部分接触并形成半导体鳍片。

50. 发明授权

US08889497B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08889497B2
公开(公告)日：2014-11-18
申请号：US13730640
申请日：2012-12-28
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chi-Yuan Chen , Teng-Chun Tsai , Kuo-Yin Lin , Wan-Chun Pan , Hsiang-Pi Chang , Shi Ning Ju , Yen-Yu Chen , Hongfa Luan , Kuo-Cheng Ching
IPC分类号： H01L21/84 , H01L29/78 , H01L29/66
CPC分类号： H01L29/42356 , H01L29/16 , H01L29/20 , H01L29/24 , H01L29/42392 , H01L29/4966 , H01L29/66795 , H01L29/785 , H01L29/7855
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes partially manufacturing a fin field effect transistor (FinFET) including a semiconductor fin comprising a first semiconductive material and a second semiconductive material disposed over the first semiconductive material. A top portion of the second semiconductive material of the semiconductor fin is removed, and a top portion of the first semiconductive material is exposed. A top portion first semiconductive material is removed from beneath the second semiconductive material. The first semiconductive material and the second semiconductive material are oxidized, forming a first oxide comprising a first thickness on the first semiconductive material and a second oxide comprising a second thickness on the second semiconductive material, the first thickness being greater than the second thickness. The second oxide is removed from the second semiconductive material, and manufacturing of the FinFET is completed.
摘要翻译：公开了半导体器件及其制造方法。在一些实施例中，制造半导体器件的方法包括部分地制造鳍状场效应晶体管（FinFET），其包括半导体鳍片，其包括第一半导体材料和设置在第一半导体材料上的第二半导体材料。去除半导体鳍片的第二半导体材料的顶部，暴露第一半导体材料的顶部。从第二半导体材料下方移除顶部第一半导体材料。第一半导体材料和第二半导体材料被氧化，在第一半导体材料上形成包括第一厚度的第一氧化物和在第二半导体材料上形成第二厚度的第二氧化物，第一厚度大于第二厚度。第二氧化物从第二半导体材料中去除，FinFET的制造完成。

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