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41. 发明授权

US09070688B2 Method of patterning a semiconductor device having improved spacing and shape control and a semiconductor device 有权
标题翻译：图案化具有改进的间隔和形状控制的半导体器件的方法和半导体器件
公开(公告)号：US09070688B2
公开(公告)日：2015-06-30
申请号：US14053973
申请日：2013-10-15
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Jhun Hua Chen , Yu-Lung Tung , Chi-Tien Chen , Hua-Tai Lin , Hsiang-Lin Chen , Hung-Chang Hsieh , Yi-Fan Chen
IPC分类号： H01L21/8242 , H01L23/528 , H01L21/8238 , H01L21/768 , H01L21/311
CPC分类号： H01L23/528 , H01L21/31144 , H01L21/76897 , H01L21/8238 , H01L21/823871 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate, a first active region in the semiconductor substrate, and a second active region in the semiconductor substrate. The semiconductor device further includes a first conductive line over the semiconductor substrate electrically connected to the first active region and having a first end face adjacent to the second active region, and the first end face having an image log slope of greater than 15 μm−1.
摘要翻译：半导体器件包括半导体衬底，半导体衬底中的第一有源区和半导体衬底中的第二有源区。所述半导体器件还包括在所述半导体衬底之上的与所述第一有源区电连接并且具有与所述第二有源区相邻的第一端面的第一导电线，并且所述第一端面的图像对数斜率大于15μm-1 。

42. 发明申请

US20150147867A1 Method Of Making a FinFET Device 有权
标题翻译：制造FinFET器件的方法
公开(公告)号：US20150147867A1
公开(公告)日：2015-05-28
申请号：US14088861
申请日：2013-11-25
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ming-Feng Shieh , Hung-Chang Hsieh , Han-Wei Wu
IPC分类号： H01L21/308 , H01L21/762 , H01L21/306
CPC分类号： H01L21/823431 , H01L21/30604 , H01L21/3086 , H01L21/3088 , H01L21/31055 , H01L21/823821 , H01L21/845 , H01L29/66545 , H01L29/66795
摘要： A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. A plurality of mandrel features are formed on a substrate. First spacers are formed along sidewalls of the mandrel feature and second spacers are along sidewalls of the first spacers. Two back-to-back adjacent second spacers separate by a gap in a first region and merge together in a second region of the substrate. A dielectric feature is formed in the gap and a dielectric mesa is formed in a third region of the substrate. A first subset of the first spacer is removed in a first cut. Fins and trenches are formed by etching the substrate using the first spacer and the dielectric feature as an etch mask.
摘要翻译：公开了制造鳍状场效应晶体管（FinFET）器件的方法。多个心轴特征形成在基底上。第一间隔件沿着心轴特征的侧壁形成，第二间隔件沿着第一间隔件的侧壁。两个背对背相邻的第二间隔件通过第一区域中的间隙分开，并在基板的第二区域中合并在一起。在间隙中形成电介质特征，并且在衬底的第三区域中形成电介质台面。在第一切割中去除第一间隔物的第一子集。通过使用第一间隔件和电介质特征作为蚀刻掩模蚀刻衬底来形成焊盘和沟槽。

43. 发明授权

US08975129B1 Method of making a FinFET device 有权
标题翻译：制造FinFET器件的方法
公开(公告)号：US08975129B1
公开(公告)日：2015-03-10
申请号：US14079313
申请日：2013-11-13
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ming-Feng Shieh , Hung-Chang Hsieh , Chen-Yu Chen
IPC分类号： H01L21/8238 , H01L21/308 , H01L21/764 , H01L21/762
CPC分类号： H01L21/3086 , H01L21/76224 , H01L21/764 , H01L21/823431 , H01L21/823821
摘要： A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. A plurality of mandrel features are formed on a substrate. First spacers are formed along sidewalls of the mandrel feature and second spacers are along sidewalls of the first spacers. Two back-to-back adjacent second spacers separate by a gap in a first region and merge together in a second region of the substrate. A dielectric feature is formed in the gap and a dielectric mesa is formed in a third region of the substrate. A first subset of the first spacer is removed in a fine cut. Fins and trenches are formed by etching the substrate using the first spacer and the dielectric feature as an etch mask.
摘要翻译：公开了制造鳍状场效应晶体管（FinFET）器件的方法。多个心轴特征形成在基底上。第一间隔件沿着心轴特征的侧壁形成，第二间隔件沿着第一间隔件的侧壁。两个背对背相邻的第二间隔件通过第一区域中的间隙分开，并在基板的第二区域中合并在一起。在间隙中形成电介质特征，并且在衬底的第三区域中形成电介质台面。以细切割方式移除第一间隔物的第一子集。通过使用第一间隔件和电介质特征作为蚀刻掩模蚀刻衬底来形成焊盘和沟槽。

44. 发明申请

US20150064916A1 Method For Integrated Circuit Patterning 有权
标题翻译：集成电路图案化方法
公开(公告)号：US20150064916A1
公开(公告)日：2015-03-05
申请号：US14014771
申请日：2013-08-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ming-Feng Shieh , Ru-Gun Liu , Hung-Chang Hsieh , Tien-I Bao , Chung-Ju Lee , Shau-Lin Shue
IPC分类号： H01L21/308
CPC分类号： H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L21/76816 , H01L29/66795
摘要： A method of forming a target pattern includes forming a first trench in a substrate with a cut mask; forming a first plurality of lines over the substrate with a first main mask, wherein the first main mask includes at least one line that overlaps the first trench and is thereby cut into at least two lines by the first trench; forming a spacer layer over the substrate and the first plurality of lines and over sidewalls of the first plurality of lines; forming a patterned material layer over the spacer layer with a second main mask thereby the patterned material layer and the spacer layer collectively define a second plurality of trenches; removing at least a portion of the spacer layer to expose the first plurality of lines; and removing the first plurality of lines thereby resulting a patterned spacer layer over the substrate.
摘要翻译：形成目标图案的方法包括：在切割掩模的基板中形成第一沟槽; 用第一主掩模在衬底上形成第一多条线，其中第一主掩模包括与第一沟槽重叠的至少一条线，由此由第一沟槽切割成至少两条线; 在所述基板上形成间隔层，并且在所述第一多条线路中的所述第一多条线路和所述侧壁上形成间隔层; 通过第二主掩模在间隔层上形成图案化材料层，由此图案化材料层和间隔层共同限定第二多个沟槽; 去除所述间隔层的至少一部分以暴露所述第一多条线; 并且去除第一多个线，从而在衬底上形成图案化间隔层。

45. 发明申请

US20150056724A1 INTEGRATED CIRCUIT LAYOUT AND METHOD WITH DOUBLE PATTERNING 有权
标题翻译：集成电路布局和方法双重方式
公开(公告)号：US20150056724A1
公开(公告)日：2015-02-26
申请号：US13971363
申请日：2013-08-20
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ming-Feng Shieh , Ru-Gun Liu , Hung-Chang Hsieh , Tsai-Sheng Gau , Yao-Ching Ku
IPC分类号： H01L21/308 , H01L21/66
CPC分类号： H01L22/12 , H01L21/266 , H01L21/3086 , H01L21/76224 , H01L21/823431 , H01L21/845 , Y10S438/942
摘要： The present disclosure provides one embodiment of a method for an integrated circuit (IC). The method includes forming a mandrel pattern on a substrate by a first lithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask.
摘要翻译：本公开提供了用于集成电路（IC）的方法的一个实施例。该方法包括通过第一光刻工艺在基板上形成心轴图案; 在心轴图案的侧壁上形成第一间隔图案; 去除心轴图案; 在所述第一间隔图案的侧壁上形成第二间隔图案; 去除第一间隔图案; 并使用第二间隔图案作为蚀刻掩模蚀刻该衬底。

46. 发明申请

US20140268074A1 Lithography System with an Embedded Cleaning Module 审中-公开
标题翻译：带有嵌入式清洁模块的平版印刷系统
公开(公告)号：US20140268074A1
公开(公告)日：2014-09-18
申请号：US14168114
申请日：2014-01-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shang-Chieh Chien , Jeng-Horng Chen , Jui-Ching Wu , Chia-Chen Chen , Hung-Chang Hsieh , Chi-Lun Lu , Chia-Hao Yu , Shih-Ming Chang , Anthony Yen
IPC分类号： G03F7/20
CPC分类号： G03F7/70925 , G03F7/70741
摘要： The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.
摘要翻译：本公开提供了一种光刻系统。光刻系统包括：曝光模块，被配置为使用固定在掩模台上的掩模执行光刻曝光工艺; 以及集成在所述曝光模块中并被设计成使用吸引机构来清洁所述掩模和所述掩模台中的至少一个的清洁模块。

47. 发明授权

US09929153B2 Method of making a FinFET device 有权
公开(公告)号：US09929153B2
公开(公告)日：2018-03-27
申请号：US14057183
申请日：2013-10-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ming-Feng Shieh , Weng-Hung Tseng , Tzung-Hua Lin , Hung-Chang Hsieh
IPC分类号： H01L21/8234 , H01L27/088 , H01L21/84
CPC分类号： H01L27/0886 , H01L21/823431 , H01L21/823481 , H01L21/845
摘要： A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. The method includes forming a mandrel features over a substrate, the mandrel feature and performing a coarse cut to remove one or more mandrel features to form a coarse space. After the coarse cut, the substrate is etched by using the mandrel features, with the coarse space as an etch mask, to form fins. A spacer layer is deposited to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the coarse space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the coarse space. A fine cut is performed to remove a portion of one or more mandrel features to form an end-to-end space. An isolation trench is formed in the end-to-end space and the coarse space.

48. 发明授权

US09875892B2 Method of forming a photoresist layer 有权
公开(公告)号：US09875892B2
公开(公告)日：2018-01-23
申请号：US14707387
申请日：2015-05-08
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chun-Wei Chang , Chih-Chien Wang , Wang-Pen Mo , Hung-Chang Hsieh
IPC分类号： B05D3/12 , H01L21/02 , H01L21/027 , H01L21/67 , B05D1/00
CPC分类号： H01L21/02282 , B05D1/005 , G03F7/091 , G03F7/162 , H01L21/0271 , H01L21/0276 , H01L21/6715
摘要： A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material.

49. 发明授权

US09703918B2 Two-dimensional process window improvement 有权
公开(公告)号：US09703918B2
公开(公告)日：2017-07-11
申请号：US14658947
申请日：2015-03-16
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Wei-De Ho , Chi-Yuan Sun , Ya Hui Chang , Hung-Chang Hsieh
IPC分类号： G03F1/36 , G03F1/44 , G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： A method of optimizing a semiconductor mask layout is provided. The method includes accessing a digital file comprising the semiconductor mask layout, accessing processing condition parameters describing process conditions, receiving a request from a user of a mask layout system to initiate a semiconductor mask layout optimization process, applying a set of rules to insert an array of assist features into the semiconductor mask layout, and updating the digital file. The semiconductor mask layout includes a plurality of parallel mask features, wherein pairs of the parallel mask features share an end-to-end region between the parallel mask features of each pair, with an imaginary axis bisecting the end-to-end regions. Each assist feature is located proximate to at least one end-to-end region, and the imaginary axis intersects each assist feature. Related photomasks, design layout systems, and computer-readable media are also provided.

50. 发明申请

US20170090299A1 Lithography Alignment Marks 有权
公开(公告)号：US20170090299A1
公开(公告)日：2017-03-30
申请号：US14868532
申请日：2015-09-29
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ching-Huang Chen , Hung-Chang Hsieh , Kuei-Liang Lu , Ya Hui Chang
IPC分类号： G03F7/20
CPC分类号： G03F7/70141 , G03F7/70633 , G03F9/7076 , H01L22/12 , Y10S438/975
摘要： A device for semiconductor fabrication includes a substrate and a layer formed over the substrate, wherein the layer includes an alignment mark. The alignment mark includes a first plurality of elongated members that are oriented lengthwise along a first direction and are distributed along a second direction. The alignment mark further includes a second plurality of elongated members that are oriented lengthwise along a third direction perpendicular to the first direction and are distributed along the second direction, wherein the second direction is different from each of the first and third directions.

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