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41. 发明授权

US07557388B2 MOSFET formed on a strained silicon layer 有权
标题翻译：形成在应变硅层上的MOSFET
公开(公告)号：US07557388B2
公开(公告)日：2009-07-07
申请号：US11398118
申请日：2006-04-05
申请人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
发明人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
IPC分类号： H01L31/00 , H01L35/26 , H01L31/117
CPC分类号： C30B29/06 , C30B15/00
摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.
摘要翻译：公开了一种形成在应变硅层上的半导体器件及其制造方法。根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

42. 发明授权

US07492006B2 Semiconductor transistors having surface insulation layers and methods of fabricating such transistors 失效
标题翻译：具有表面绝缘层的半导体晶体管和制造这种晶体管的方法
公开(公告)号：US07492006B2
公开(公告)日：2009-02-17
申请号：US11215217
申请日：2005-08-30
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Sang-Jin Hyun , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Sang-Jin Hyun , Guk-Hyon Yon
IPC分类号： H01L23/62
CPC分类号： H01L29/4983 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/7881 , H01L29/792
摘要： Semiconductor devices having a transistor and methods of fabricating such devices are disclosed. The device may include a gate pattern formed on a substrate, spacers formed on sidewalls of the gate pattern, a surface insulation layer that may contact the substrate is interposed between the spacers and the substrate. An inversion layer is provided in the surface region of the substrate under the surface insulation layer. The surface insulation layer is formed of a material generating large quantities of surface states at an interface between the substrate and the surface insulation layer.
摘要翻译：公开了具有晶体管的半导体器件及其制造方法。器件可以包括形成在衬底上的栅极图案，形成在栅极图案的侧壁上的间隔物，可以接触衬底的表面绝缘层插入在衬垫和衬底之间。在表面绝缘层下方的基板的表面区域设置反转层。表面绝缘层由在基板和表面绝缘层之间的界面处产生大量表面状态的材料形成。

43. 发明授权

US07364990B2 Epitaxial crystal growth process in the manufacturing of a semiconductor device 有权
标题翻译：外延晶体生长工艺制造半导体器件
公开(公告)号：US07364990B2
公开(公告)日：2008-04-29
申请号：US11301029
申请日：2005-12-13
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： C30B21/36
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/02647
摘要： First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection structure of a material having an amorphous state is formed on a portion of the insulation layer located between the first and second preliminary epitaxial layers. The material having an amorphous state is then changed into material having a single-crystalline state. Thus, portions of the first and second epitaxial layers are connected to each other through the connection structure so that the epitaxial layers and the connection structure constitute a single-crystalline structure layer that is free of voids for use as a channel layer or the like of a semiconductor device.
摘要翻译：第一和第二初步外延层从绝缘层的开口中的单晶种子生长直到第一和第二外延层彼此连接。当正在生长第一和第二初步外延层时，在位于第一和第二初步外延层之间的绝缘层的一部分上形成具有非晶状态的材料的连接结构。然后将具有非晶态的材料变成具有单晶态的材料。因此，第一外延层和第二外延层的部分通过连接结构彼此连接，使得外延层和连接结构构成无空隙的单晶结构层，用作沟道层等半导体器件。

44. 发明申请

US20070123062A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070123062A1
公开(公告)日：2007-05-31
申请号：US11605092
申请日：2006-11-28
申请人： Sung-Kwan Kang , Jong-Wook Lee , Yong-Hoon Son , Yu-Gyun Shin , Jun-Ho Lee
发明人： Sung-Kwan Kang , Jong-Wook Lee , Yong-Hoon Son , Yu-Gyun Shin , Jun-Ho Lee
IPC分类号： H01L21/336 , H01L29/76 , H01L21/00
CPC分类号： H01L29/66795 , H01L29/7851
摘要： In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewall. The opening is formed through an insulation structure located on a substrate. The plug and the channel structure comprise a material in a single crystalline state that is changed from an amorphous state by an irradiation of a laser beam. The channel structure is doped with impurities such as boron, phosphorus or arsenic.
摘要翻译：在半导体器件和半导体器件的制造方法中，形成插头和沟道结构。塞子填充开口并且通道结构从插头向上延伸。通道结构具有基本垂直的侧壁。开口通过位于基板上的绝缘结构形成。塞子和通道结构包括通过激光束的照射从非晶状态改变的单晶状态的材料。通道结构掺杂有杂质如硼，磷或砷。

45. 发明申请

US20070057333A1 MOS transistor and method of manufacturing the same 审中-公开
标题翻译： MOS晶体管及其制造方法
公开(公告)号：US20070057333A1
公开(公告)日：2007-03-15
申请号：US11519063
申请日：2006-09-12
申请人： Hong-Bae Park , Yu-Gyun Shin
发明人： Hong-Bae Park , Yu-Gyun Shin
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/513 , H01L21/28035 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/4925 , H01L29/517
摘要： Example embodiments relate to a metal-oxide-semiconductor (MOS) transistor and a method of manufacturing the MOS transistor. In a MOS transistor and a method of manufacturing the same, a gate insulation layer may be formed on the channel region of the substrate, and may further include metal oxide or metal silicate. A buffer layer may be formed on the gate insulation layer. The buffer layer may further include any one selected from the group including silicon nitride, aluminum nitride, undoped polysilicon and combinations thereof. A gate conductive layer may be formed on the buffer layer and may further include polysilicon. The buffer layer may retard or prevent a reaction between the gate conductive layer and the gate insulation layer. Source/drain regions may be further formed at surface portions of the substrate and doped with impurities. A channel region may also be further formed at the surface portion of the substrate between the source/drain regions.
摘要翻译：示例性实施例涉及金属氧化物半导体（MOS）晶体管和制造MOS晶体管的方法。在MOS晶体管及其制造方法中，可以在衬底的沟道区上形成栅极绝缘层，还可以包括金属氧化物或金属硅酸盐。可以在栅极绝缘层上形成缓冲层。缓冲层可以进一步包括从包括氮化硅，氮化铝，未掺杂的多晶硅及其组合的组中选择的任一种。栅极导电层可以形成在缓冲层上，并且还可以包括多晶硅。缓冲层可以延迟或防止栅极导电层和栅极绝缘层之间的反应。源极/漏极区域可以进一步形成在衬底的表面部分并掺杂杂质。还可以在源极/漏极区之间的衬底的表面部分处进一步形成沟道区。

46. 发明申请

US20060292880A1 Methods of fabricating p-type transistors including germanium channel regions and related devices 有权
标题翻译：制造包括锗通道区域和相关器件的p型晶体管的方法
公开(公告)号：US20060292880A1
公开(公告)日：2006-12-28
申请号：US11447436
申请日：2006-06-06
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： H02N6/00 , H01L21/302
CPC分类号： H01L29/1054 , H01L21/02532 , H01L21/02675 , H01L21/8221 , H01L27/0688 , H01L27/11 , H01L27/1104 , H01L29/16
摘要： A method of fabricating a transistor device includes forming a non-crystalline germanium layer on a seed layer. The non-crystalline germanium layer is selectively locally heated to about a melting point thereof to form a single-crystalline germanium layer on the seed layer. The non-crystalline germanium layer may be selectively locally heated, for example, by applying a laser to a portion of the non-crystalline germanium layer. Related devices are also discussed.
摘要翻译：制造晶体管器件的方法包括在种子层上形成非结晶锗层。选择性地将非结晶锗层局部加热至其熔点，以在籽晶层上形成单晶锗层。可以例如通过对非晶锗层的一部分施加激光来选择性地局部加热非晶锗层。还讨论了相关设备。

47. 发明申请

US20060118876A1 Fin field effect transistor and method of manufacturing the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US20060118876A1
公开(公告)日：2006-06-08
申请号：US11292261
申请日：2005-11-30
申请人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
发明人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
IPC分类号： H01L21/338 , H01L29/76
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7854
摘要： In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern. Internal stresses that can be generated in sidewalls of the active pattern are sufficiently released and an original shape of the first silicon nitride pattern remains unchanged, thereby improving electrical characteristics of the fin FET.
摘要翻译：在鳍状场效应晶体管（FET）中，有源图案在垂直方向上从基板突出，并且在第一水平方向上延伸穿过基板。第一氮化硅图案形成在有源图案上，并且第一氧化物图案和第二氮化硅图案依次形成在衬底上和活性图案的下部的侧壁上。在第二氮化硅图案上形成器件隔离层，器件隔离层的顶表面与氧化物图案和第二氮化硅图案的顶表面共面。在第一氧化物图案和第二氮化硅图案之间形成具有相对于第二氮化硅图案的蚀刻选择性的缓冲图案。可以在有源图案的侧壁中产生的内部应力被充分地释放，并且第一氮化硅图案的原始形状保持不变，从而改善了鳍式FET的电特性。

48. 发明申请

US20060081895A1 Semiconductor device having fin transistor and planar transistor and associated methods of manufacture 有权
公开(公告)号：US20060081895A1
公开(公告)日：2006-04-20
申请号：US11244136
申请日：2005-10-06
申请人： Deok-Huyng Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
发明人： Deok-Huyng Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
IPC分类号： H01L29/76
CPC分类号： H01L29/7851 , H01L21/823431 , H01L21/84 , H01L27/1203 , H01L29/66795
摘要： Disclosed is a fin transistor and a planar transistor and a method of forming the same. The fin transistor and the planar transistor are formed to have gate electrodes with similar thicknesses by selectively recessing a semiconductor substrate in a planar region where the planar transistor is formed.

49. 发明授权

US08501611B2 Methods of forming integrated circuit devices having electrically conductive layers therein with partially nitridated sidewalls 有权
标题翻译：形成其中具有部分氮化侧壁的导电层的集成电路器件的方法
公开(公告)号：US08501611B2
公开(公告)日：2013-08-06
申请号：US13551251
申请日：2012-07-17
申请人： Jeong-Do Ryu , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Dong-Chan Kim , Jong-Ryeol Yoo , Seong-Hoon Jeong , Jong-Hoon Kang
发明人： Jeong-Do Ryu , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Dong-Chan Kim , Jong-Ryeol Yoo , Seong-Hoon Jeong , Jong-Hoon Kang
IPC分类号： H01L21/3205
CPC分类号： H01L21/28061 , H01L21/28247 , H01L21/3211 , H01L21/32137 , H01L21/32139 , H01L27/10873 , H01L27/11 , H01L27/1104
摘要： Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.
摘要翻译：形成集成电路器件的方法包括在衬底上形成含硅的导电层，并在导电层上形成掩模图案。使用掩模图案作为蚀刻掩模，选择性地蚀刻导电层以限定其上的第一侧壁。可以将导电层的第一侧壁暴露于氮等离子体，从而在第一侧壁上形成第一氮化硅层。然后再次选择性地蚀刻导电层以暴露其上没有第一氮化硅层的第二侧壁。在选择性蚀刻导电层的第二步骤期间，掩模图案可以再次用作蚀刻掩模。

50. 发明授权

US08470703B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08470703B2
公开(公告)日：2013-06-25
申请号：US13105195
申请日：2011-05-11
申请人： Byung-Hak Lee , Yu-Gyun Shin , Sang-Woo Lee , Sun-Ghil Lee , Jin-Bum Kim , Joon-Gon Lee
发明人： Byung-Hak Lee , Yu-Gyun Shin , Sang-Woo Lee , Sun-Ghil Lee , Jin-Bum Kim , Joon-Gon Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518 , H01L21/823807 , H01L21/823814
摘要： Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time. The sequentially performed first and second heat-treatment processes convert the Ni metal layer on the source and drain regions into a NiSi layer on the source and drain regions and a NiSi2 layer between the NiSi layer and the source and drain regions.
摘要翻译：形成半导体器件的方法包括提供具有包括晶体管的源极和漏极区域的区域的衬底。在包括源极和漏极区域的衬底区域上形成镍（Ni）金属膜。执行第一热处理工艺，包括以第一斜率从第一温度至第二温度加热包括金属膜的基板，并将包含金属膜的基板在第二温度下保持第一时间段。然后执行第二热处理工艺，包括以第二斜率从第三温度至第四温度加热包括金属膜的衬底，并将衬底保持在第四温度第二时间段。第四温度与第二温度不同，第二时间段与第一时间段不同。依次执行的第一和第二热处理工艺将源极和漏极区域上的Ni金属层转换成源极和漏极区域上的NiSi层以及NiSi层与源极和漏极区域之间的NiSi 2层。

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