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41. 发明授权

US08049114B2 Package substrate with a cavity, semiconductor package and fabrication method thereof 有权
标题翻译：具有空腔的封装衬底，半导体封装及其制造方法
公开(公告)号：US08049114B2
公开(公告)日：2011-11-01
申请号：US12408719
申请日：2009-03-22
申请人： Kuo-Ching Chen , Tsung-Yuan Chen , Cheng-Pin Chien
发明人： Kuo-Ching Chen , Tsung-Yuan Chen , Cheng-Pin Chien
IPC分类号： H05K1/03
CPC分类号： H01L23/3128 , H01L21/4857 , H01L21/56 , H01L23/13 , H01L23/49822 , H01L23/49827 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12041 , H01L2924/14 , H01L2924/15331 , H01L2924/181 , H05K1/183 , H05K1/186 , H05K3/06 , H05K3/427 , H05K3/4602 , H05K3/4652 , H05K3/4697 , H05K2201/0361 , H05K2201/10674 , H05K2201/10734 , H05K2203/308 , H01L2924/00012 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2224/0401
摘要： A method of making a package substrate includes providing a cladding sheet comprising a first metal layer, a second metal layer and an intermediate layer between the first and second metal layers; etching away a portion of the first metal layer to expose a portion of the intermediate layer thereby forming a metal island body; laminating a first copper clad on the cladding sheet comprising a first copper foil and a first insulating layer; patterning the first copper foil to form a first circuit trace; patterning the second metal layer to form a second circuit trace; removing the metal island body to form a cavity in the first insulating layer; and removing the intermediate layer from bottom of the cavity.
摘要翻译：制造封装衬底的方法包括提供包括第一金属层，第二金属层和第一和第二金属层之间的中间层的覆层片; 蚀刻掉第一金属层的一部分以暴露中间层的一部分，从而形成金属岛体; 在包括第一铜箔和第一绝缘层的包层片上层叠第一铜包层; 图案化第一铜箔以形成第一电路迹线; 图案化第二金属层以形成第二电路迹线; 去除所述金属岛体以在所述第一绝缘层中形成空腔; 以及从腔的底部去除中间层。

42. 发明申请

US20080280032A1 PROCESS OF EMBEDDED CIRCUIT STRUCTURE 有权
标题翻译：嵌入式电路结构的过程
公开(公告)号：US20080280032A1
公开(公告)日：2008-11-13
申请号：US11934500
申请日：2007-11-02
申请人： Tsung-Yuan Chen , Chun-Chien Chen
发明人： Tsung-Yuan Chen , Chun-Chien Chen
IPC分类号： B28B19/00
CPC分类号： H05K3/205 , H05K3/382 , H05K2201/0355 , H05K2203/1536 , H05K2203/1572
摘要： A process of an embedded circuit structure is provided. A complex metal layer, a prepreg, a supporting board, another prepreg and another complex metal layer are laminated together, wherein each of the complex metal layers has an inner metal layer and an outer metal layer stacked on the inner metal layer, the roughness of the outer surfaces of the inner metal layers is less than the roughness of the second outer surfaces of the outer metal layers, and the outer surfaces of the outer metal layers after laminating are exposed outwards. Each of two patterned photoresist layers is respectively formed on the outer surfaces of the outer metal layers. A metal material is created on portions of the outer surfaces of the outer metal layers not covered by the patterned photoresist layers to form two patterned circuit layers. The patterned photoresist layers are then removed to form a laminating structure.
摘要翻译：提供了一种嵌入式电路结构的过程。将复合金属层，预浸料坯，支撑基板，其他预浸料坯和另一复合金属层层压在一起，其中，每个复合金属层具有堆叠在内金属层上的内金属层和外金属层，粗糙度内金属层的外表面小于外金属层的第二外表面的粗糙度，层压后的外金属层的外表面向外露出。两个图案化的光致抗蚀剂层中的每一个分别形成在外部金属层的外表面上。在不被图案化的光致抗蚀剂层覆盖的外部金属层的外表面的部分上形成金属材料，以形成两个图案化的电路层。然后去除图案化的光致抗蚀剂层以形成层压结构。

43. 发明授权

US08604359B2 Package substrate and fabrication method thereof 有权
标题翻译：封装基板及其制造方法
公开(公告)号：US08604359B2
公开(公告)日：2013-12-10
申请号：US13241264
申请日：2011-09-23
申请人： Tsung-Yuan Chen , Shih-Lian Cheng
发明人： Tsung-Yuan Chen , Shih-Lian Cheng
IPC分类号： H05K1/11
CPC分类号： H05K3/4038 , H01L21/4857 , H01L23/49822 , H01L24/16 , H01L24/81 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2224/83102 , H01L2924/12042 , H01L2924/15311 , H05K3/10 , H05K3/3436 , H05K3/4644 , H05K3/4694 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165 , H01L2924/014 , H01L2924/00
摘要： A package substrate includes a core board, a first dielectric layer, a second circuit pattern, a first solder mask and an insulating layer. A first circuit pattern is disposed on a first surface of the core board. The first dielectric layer covers the first circuit pattern. The second circuit pattern is located on the first dielectric layer and the second circuit pattern includes an interconnection circuit pattern within a chip mounting area. The first solder mask covers a portion of the second circuit pattern outside the chip mounting area. The insulating layer covers the chip mounting area and the interconnection circuit pattern. A plurality of embedded bump pads are located on an upper surface of the insulating layer.
摘要翻译：封装基板包括芯板，第一介电层，第二电路图案，第一焊料掩模和绝缘层。第一电路图案设置在芯板的第一表面上。第一电介质层覆盖第一电路图案。第二电路图案位于第一电介质层上，第二电路图案包括在芯片安装区域内的互连电路图案。第一焊接掩模覆盖芯片安装区域外的第二电路图案的一部分。绝缘层覆盖芯片安装区域和互连电路图案。多个嵌入式凸块焊盘位于绝缘层的上表面上。

44. 发明授权

US07931818B2 Process of embedded circuit structure 有权
标题翻译：嵌入式电路结构的过程
公开(公告)号：US07931818B2
公开(公告)日：2011-04-26
申请号：US11934500
申请日：2007-11-02
申请人： Tsung-Yuan Chen , Chun-Chien Chen
发明人： Tsung-Yuan Chen , Chun-Chien Chen
IPC分类号： H01B13/00
CPC分类号： H05K3/205 , H05K3/382 , H05K2201/0355 , H05K2203/1536 , H05K2203/1572
摘要： A process of an embedded circuit structure is provided. A complex metal layer, a prepreg, a supporting board, another prepreg and another complex metal layer are laminated together, wherein each of the complex metal layers has an inner metal layer and an outer metal layer stacked on the inner metal layer, the roughness of the outer surfaces of the inner metal layers is less than the roughness of the second outer surfaces of the outer metal layers, and the outer surfaces of the outer metal layers after laminating are exposed outwards. Each of two patterned photoresist layers is respectively formed on the outer surfaces of the outer metal layers. A metal material is created on portions of the outer surfaces of the outer metal layers not covered by the patterned photoresist layers to form two patterned circuit layers. The patterned photoresist layers are then removed to form a laminating structure.
摘要翻译：提供了一种嵌入式电路结构的过程。将复合金属层，预浸料坯，支撑基板，其他预浸料坯和另一复合金属层层压在一起，其中每个复合金属层具有层叠在内金属层上的内金属层和外金属层，其粗糙度内金属层的外表面小于外金属层的第二外表面的粗糙度，层压后的外金属层的外表面向外露出。两个图案化的光致抗蚀剂层中的每一个分别形成在外部金属层的外表面上。在不被图案化的光致抗蚀剂层覆盖的外部金属层的外表面的部分上形成金属材料，以形成两个图案化的电路层。然后去除图案化的光致抗蚀剂层以形成层压结构。

45. 发明授权

US07774932B2 Circuit board process 有权
标题翻译：电路板工艺
公开(公告)号：US07774932B2
公开(公告)日：2010-08-17
申请号：US11759941
申请日：2007-06-08
申请人： Chun-Chien Chen , Tsung-Yuan Chen
发明人： Chun-Chien Chen , Tsung-Yuan Chen
IPC分类号： H01K3/10
CPC分类号： H05K3/205 , H05K3/002 , H05K3/0032 , H05K3/428 , H05K3/4602 , H05K3/4658 , H05K2201/09536 , H05K2201/09563 , H05K2201/0959 , H05K2201/096 , H05K2203/0554 , H05K2203/1152 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A circuit board process is provided. First, multiple carriers is provided, and a first conductive layer having multiple concave structures is formed on each carrier. A dielectric layer is then provided, and the carriers with the first conductive layers are laminated on a first and a second surface of the dielectric layer respectively, wherein portions of the first conductive layers are embedded in the first and second surfaces. Next, the carriers are removed. Thereafter, the first conductive layer corresponding to at least one concave is removed to expose a portion of the dielectric layer. Next, the exposed dielectric layer is removed to form an opening. A second conductive layer is then formed on the inner wall of the opening, wherein the second conductive layer is electrically connected to the first conductive layers on both sides of the dielectric layer.
摘要翻译：提供电路板工艺。首先，提供多个载体，并且在每个载体上形成具有多个凹形结构的第一导电层。然后提供电介质层，并且具有第一导电层的载体分别层叠在电介质层的第一和第二表面上，其中第一导电层的部分嵌入在第一和第二表面中。接下来，移除载体。此后，去除与至少一个凹部对应的第一导电层，以露出电介质层的一部分。接下来，去除暴露的介电层以形成开口。然后在开口的内壁上形成第二导电层，其中第二导电层与电介质层两侧的第一导电层电连接。

46. 发明授权

US09084379B2 Process for fabricating wiring board 有权
标题翻译：制造布线板的工艺
公开(公告)号：US09084379B2
公开(公告)日：2015-07-14
申请号：US13423578
申请日：2012-03-19
申请人： Tsung-Yuan Chen , Chun-Chien Chen , Cheng-Po Yu
发明人： Tsung-Yuan Chen , Chun-Chien Chen , Cheng-Po Yu
IPC分类号： H01K3/10 , H05K3/00 , H05K3/36 , H05K1/00 , H05K1/14 , H05K3/42 , H05K3/20
CPC分类号： H05K3/428 , H05K3/0032 , H05K3/0035 , H05K3/0038 , H05K3/20 , H05K3/205 , H05K2201/09509 , H05K2201/09563 , H05K2201/0969 , H05K2203/0369 , H05K2203/0376 , H05K2203/0384 , H05K2203/0554 , H05K2203/108 , H05K2203/1476 , Y10T29/49124 , Y10T29/49126
摘要： A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.
摘要翻译：提供一种制造布线板的工艺。在该过程中，形成包括携带衬底和布线层的布线承载衬底。接下来，在布线承载基板中形成至少一个盲孔。接下来，通过绝缘层将布线承载基板层叠到另一布线承载基板。绝缘层设置在布线基板的布线层之间，并且完全填充盲孔。接下来，去除部分搬运基板以露出盲孔中的绝缘层。接下来，形成连接在布线层之间的导电柱。接下来，其余的携带衬底被去除。

47. 发明申请

US20100314352A1 FABRICATING METHOD OF EMBEDDED PACKAGE STRUCTURE 有权
标题翻译：嵌入式封装结构的制作方法
公开(公告)号：US20100314352A1
公开(公告)日：2010-12-16
申请号：US12555210
申请日：2009-09-08
申请人： Tsung-Yuan Chen , Ming-Huang Ting
发明人： Tsung-Yuan Chen , Ming-Huang Ting
IPC分类号： B32B38/10 , H01B13/00
CPC分类号： H05K3/4007 , H01L21/6835 , H01L23/5389 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2221/68304 , H01L2221/68359 , H01L2221/68363 , H01L2221/68381 , H01L2221/68386 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/2919 , H01L2224/321 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/81903 , H01L2224/83005 , H01L2224/83203 , H01L2224/8385 , H01L2224/83862 , H01L2224/9211 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/12042 , H01L2924/14 , H05K1/186 , H05K1/187 , H05K3/4614 , H05K3/4647 , H05K2201/10674 , H05K2203/063 , Y10T29/49124 , Y10T29/49128 , H01L2224/81 , H01L2224/83 , H01L2224/19 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A fabricating method of an embedded package structure includes following steps. First, a first circuit structure and a second circuit structure are formed respectively on a first board and a second board which are combined to form an integrated panel. The first board and the second board are then separated. Next, an embedded element is electrically disposed on the first circuit structure. At least one conductive bump is formed on the second circuit structure. Thereafter, a semi-cured film is provided, and a laminating process is performed to laminate the first circuit structure on the first board, the semi-cured film, and the second circuit structure on the second board. The semi-cured film encapsulates the embedded element and the at least one conductive bump pierces through the semi-cured film and electrically connects the first circuit structure.
摘要翻译：嵌入式封装结构的制造方法包括以下步骤。首先，第一电路结构和第二电路结构分别形成在组合形成集成面板的第一板和第二板上。然后将第一板和第二板分开。接下来，嵌入式元件电气地布置在第一电路结构上。在第二电路结构上形成至少一个导电凸块。此后，提供半固化膜，并且进行层压工艺以将第一电路结构层压在第二板上的第一板，半固化膜和第二电路结构上。半固化膜封装嵌入元件，并且至少一个导电凸块刺穿半固化膜并电连接第一电路结构。

48. 发明申请

US20100044082A1 WIRING BOARD 审中-公开
标题翻译：接线板
公开(公告)号：US20100044082A1
公开(公告)日：2010-02-25
申请号：US12260306
申请日：2008-10-29
申请人： Chun-Chien Chen , Tsung-Yuan Chen , Cheng-Po Yu
发明人： Chun-Chien Chen , Tsung-Yuan Chen , Cheng-Po Yu
IPC分类号： H05K1/00
CPC分类号： H05K1/028 , H05K1/0366 , H05K1/0393 , H05K3/107 , H05K2201/0376 , H05K2203/302
摘要： A wiring board including two wiring layers and a flexible core layer is provided. The flexible core layer is disposed between the wiring layers, and the flexible core layer is an insulator. A flexure of the wiring board is between 0 degree and 170 degrees.
摘要翻译：提供了包括两个布线层和柔性芯层的布线板。柔性芯层设置在布线层之间，柔性芯层是绝缘体。接线板的挠曲度在0度到170度之间。

49. 发明申请

US20090205852A1 CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF 有权
标题翻译：电路板及其制造方法
公开(公告)号：US20090205852A1
公开(公告)日：2009-08-20
申请号：US12193460
申请日：2008-08-18
申请人： Chun-Chien Chen , Tsung-Yuan Chen
发明人： Chun-Chien Chen , Tsung-Yuan Chen
IPC分类号： H05K1/00 , H05K3/02
CPC分类号： H05K3/44 , H05K3/20 , H05K3/423 , H05K3/427 , H05K3/428 , H05K3/445 , H05K2201/0355 , H05K2201/0376 , H05K2201/09509 , H05K2201/09554 , H05K2201/09563 , H05K2203/0369 , Y10T29/49124 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T428/24273 , Y10T428/24917
摘要： A manufacturing method of a circuit board is provided. A metal core is provided. A conductive layer is formed on each of some carriers. The carriers and dielectric layers are laminated at both sides of the metal core to form a stacked structure. Each of the dielectric layers is located between the corresponding carrier and the metal core, and a portion of the conductive layer is embedded in the corresponding dielectric layer. Then, the carriers are removed. A blind via and/or a through via are/is formed in the stacked structure to connect the corresponding conductive layer and the metal core and/or connect the conductive layers at both sides of the metal core, wherein the through via penetrates the metal core. The conductive layer on a surface of the dielectric layer is removed.
摘要翻译：提供电路板的制造方法。提供金属芯。在一些载体的每一个上形成导电层。载体和电介质层被层叠在金属芯的两侧以形成堆叠结构。每个电介质层位于相应的载体和金属芯之间，并且导电层的一部分嵌入相应的介电层中。然后，移除载体。在堆叠结构中形成盲通孔和/或通孔，以将相应的导电层和金属芯连接和/或连接金属芯两侧的导电层，其中通孔穿过金属芯。去除介电层表面上的导电层。

50. 发明申请

US20070171621A1 CIRCUIT BOARD WITH EMBEDDED PASSIVE COMPONENT AND FABRICATING PROCESS THEREOF 有权
标题翻译：具有嵌入式被动元件的电路板及其制造工艺
公开(公告)号：US20070171621A1
公开(公告)日：2007-07-26
申请号：US11626379
申请日：2007-01-24
申请人： Tsung-Yuan Chen
发明人： Tsung-Yuan Chen
IPC分类号： H05K7/00 , H05K3/10
CPC分类号： H05K1/162 , H05K1/165 , H05K1/167 , H05K3/4611 , H05K2201/0352 , H05K2201/0355 , H05K2201/0376 , H05K2201/09236 , H05K2201/09509 , H05K2201/09881 , H05K2203/0361 , H05K2203/0723 , Y10T29/49155 , Y10T156/1028
摘要： A process for fabricating a circuit board with an embedded passive component is provided. First, an electrode-patterned layer having electrodes is formed on a surface of a conductive layer. Then, a passive component material is filled in the intervals between the electrodes. Then, the conductive layer and the electrode-patterned layer are laminated to a dielectric layer, wherein the electrode-patterned layer is embedded in the dielectric layer. Next, the conductive layer is patterned to form a circuit layer.
摘要翻译：提供了一种用于制造具有嵌入式无源元件的电路板的工艺。首先，在导电层的表面上形成具有电极的电极图案层。然后，在电极之间的间隔中填充无源元件材料。然后，将导电层和电极图案层层压到电介质层，其中电极图案层被嵌入在电介质层中。接下来，对导电层进行图案化以形成电路层。

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