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41. 发明申请

US20060273384A1 Structure for avalanche improvement of ultra high density trench MOSFET 审中-公开
标题翻译：超高密度沟槽MOSFET雪崩改进的结构
公开(公告)号：US20060273384A1
公开(公告)日：2006-12-07
申请号：US11236007
申请日：2005-09-26
申请人： Fwu-Iuan Hshieh
发明人： Fwu-Iuan Hshieh
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L24/26 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L24/85 , H01L29/41766 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L2224/05624 , H01L2224/05655 , H01L2224/371 , H01L2224/37124 , H01L2224/37144 , H01L2224/37147 , H01L2224/37155 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48247 , H01L2224/48472 , H01L2224/48624 , H01L2224/48655 , H01L2224/48724 , H01L2224/48755 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/83801 , H01L2224/85 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/0132 , H01L2924/0133 , H01L2924/04941 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/20755 , H01L2924/2076 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： A trenched metal oxide semiconductor field effect transistor (MOSFET) cell that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a source-body contact trench opened with sidewalls substantially extend vertically relative to a top surface into the source and body regions and filled with contact metal plug. A body-resistance reduction region doped with body-doped is formed to surround the source-body contact trench to reduce a body-region resistance between the source-body contact metal and the trenched gate to improve an avalanche capability.
摘要翻译：沟槽金属氧化物半导体场效应晶体管（MOSFET）单元，其包括被包围在设置在基板的底表面上的漏极区域上方的体区域中的源极区域包围的沟槽栅极。 MOSFET单元还包括源体接触沟槽，侧壁基本上相对于顶表面垂直地延伸到源区和主体区域中并且用接触金属插塞填充。形成掺杂有体掺杂的体电阻降低区域以围绕源体接触沟槽，以减少源体接触金属和沟槽栅极之间的体区电阻，以改善雪崩能力。

42. 发明授权

US07049668B1 Gate contacting scheme of a trench MOSFET structure 失效
标题翻译：沟槽MOSFET结构的栅极接触方案
公开(公告)号：US07049668B1
公开(公告)日：2006-05-23
申请号：US09139935
申请日：1998-08-25
申请人： Fwu-Iuan Hshieh
发明人： Fwu-Iuan Hshieh
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L2224/05624 , H01L2224/0603 , H01L2224/48464 , H01L2224/49111 , H01L2224/49431 , H01L2924/01078 , H01L2924/01322 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： A trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure includes crisscrossing trenches formed in a semiconductor substrate. The trenches include inner surfaces filled with conductive material which is electrically separated from the substrate by insulating material. The conductive material is in contact with an overlying first metal layer through a plurality of first contact openings formed in a first insulating layer which is sandwiched between the first metal layer and the trenches. The conductive material in the trenches and the first metal layer constitute the gate of the MOSFET structure. There is also a second metal layer in contact with a source layer formed in the substrate through a plurality of second contact openings formed in a second insulating layer which is sandwiched between the first metal layer and the second metal layer. The second metal layer and the source layer constitute the source of the MOSFET structure. As arranged, the gate and source of the MOSFET structure are connected through separate metal layers on the semiconductor substrate. Consequently, each metal layer maintains higher conductivity and thus faster frequency response. The semiconductor structure formed in accordance with the invention can also assume a higher packing density with lower power-on resistance.
摘要翻译：沟槽MOSFET（金属氧化物半导体场效应晶体管）结构包括在半导体衬底中形成的交叉沟槽。沟槽包括填充有导电材料的内表面，该导电材料通过绝缘材料与衬底电分离。导电材料通过形成在夹在第一金属层和沟槽之间的第一绝缘层中的多个第一接触开口与上覆的第一金属层接触。沟槽和第一金属层中的导电材料构成MOSFET结构的栅极。还有第二金属层，其通过形成在夹在第一金属层和第二金属层之间的第二绝缘层中的多个第二接触开口与形成在基板中的源极层接触。第二金属层和源极层构成MOSFET结构的源极。如所设置的，MOSFET结构的栅极和源极通过半导体衬底上的分开的金属层连接。因此，每个金属层保持较高的导电性，从而保持更快的频率响应。根据本发明形成的半导体结构也可以具有较高的封装密度和较低的导通电阻。

43. 发明授权

US07015125B2 Trench MOSFET device with polycrystalline silicon source contact structure 失效
公开(公告)号：US07015125B2
公开(公告)日：2006-03-21
申请号：US10983490
申请日：2004-11-08
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
IPC分类号： H01L21/4763 , H01L21/336 , H01L21/8242
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/456
摘要： A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and (i) a source contact region disposed on the epitaxial layer upper surface, wherein the source contact region comprises a doped polycrystalline silicon contact region in electrical contact with the source region as well as an adjacent metal contact region in electrical contact with the source region and with the upper region.

44. 发明授权

US06884683B2 Trench DMOS transistor having a zener diode for protection from electro-static discharge 有权
标题翻译：沟槽DMOS晶体管具有用于防止静电放电的齐纳二极管
公开(公告)号：US06884683B2
公开(公告)日：2005-04-26
申请号：US10714807
申请日：2003-11-18
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L27/04 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L29/49 , H01L29/78 , H01L29/866
CPC分类号： H01L29/7813 , H01L29/4916 , H01L29/7808 , H01L2924/0002 , H01L2924/00
摘要： A trench DMOS transistor having overvoltage protection includes a substrate of a first conductivity type and a body region of a second conductivity type formed over the substrate. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and overlies the body region. A conductive electrode is deposited in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. An undoped polysilicon layer overlies a portion of the insulating layer. A plurality of cathode regions of the first conductivity type are formed in the undoped polysilicon layer. At least one anode region is in contact with adjacent ones of the plurality of cathode regions.
摘要翻译：具有过电压保护的沟槽DMOS晶体管包括形成在衬底上的第一导电类型的衬底和第二导电类型的体区。至少一个沟槽延伸穿过身体区域和衬底。绝缘层在沟槽上划线并覆盖在身体区域上。导电电极沉积在沟槽中，使其覆盖绝缘层。第一导电类型的源区形成在与沟槽相邻的体区中。未掺杂的多晶硅层覆盖绝缘层的一部分。在未掺杂多晶硅层中形成第一导电类型的多个阴极区。至少一个阳极区域与多个阴极区域中的相邻阳极区域接触。

45. 发明授权

US06762098B2 Trench DMOS transistor with embedded trench schottky rectifier 有权
标题翻译：沟槽DMOS晶体管采用嵌入式沟道肖特基整流器
公开(公告)号：US06762098B2
公开(公告)日：2004-07-13
申请号：US10448791
申请日：2003-05-30
申请人： Fwu-Iuan Hshieh , Yan Man Tsui , Koon Chong So
发明人： Fwu-Iuan Hshieh , Yan Man Tsui , Koon Chong So
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L27/0629 , H01L29/7806 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions. The integrated circuit comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower doping level than the substrate; (c) a plurality of body regions of a second conductivity type within the epitaxial layer in the transistor regions; (d) a plurality of trenches within the epitaxial layer in both the transistor regions and the rectifier regions; (e) a first insulating layer that lines the trenches; (f) a polysilicon conductor within the trenches and overlying the first insulating layer; (g) a plurality of source regions of the first conductivity type within the body regions at a location adjacent to the trenches; (h) a second insulating layer over the doped polysilicon layer in the transistor regions; and (i) an electrode layer over both the transistor regions and the rectifier regions.
摘要翻译：一种在一个或多个整流器区域内具有多个沟道肖特基势垒整流器的集成电路以及一个或多个晶体管区域内的多个沟槽DMOS晶体管。集成电路包括：（a）第一导电类型的衬底; （b）在所述衬底上的第一导电类型的外延层，其中所述外延层具有比所述衬底更低的掺杂水平; （c）晶体管区域中的外延层内的第二导电类型的多个体区; （d）在所述晶体管区域和所述整流器区域中的所述外延层内的多个沟槽;（e）对所述沟槽进行排列的第一绝缘层; （f）沟槽内的多晶硅导体并覆盖第一绝缘层; （g）在与所述沟槽相邻的位置处的所述主体区域内的所述第一导电类型的多个源极区域; （h）晶体管区域上的掺杂多晶硅层上的第二绝缘层; 和（i）在晶体管区域和整流器区域上的电极层。

46. 发明授权

US06657254B2 Trench MOSFET device with improved on-resistance 有权
公开(公告)号：US06657254B2
公开(公告)日：2003-12-02
申请号：US09999116
申请日：2001-11-21
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0878
摘要： A trench MOSFET device and method of making the same. The trench MOSFET device comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial region from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a doped region of the first conductivity type formed within the epitaxial layer between a bottom portion of the trench and the substrate, wherein the doped region has a majority carrier concentration that is lower than that of the substrate and higher than that of the epitaxial layer; (g) a body region of a second conductivity type formed within an upper portion of the epitaxial layer and adjacent the trench, wherein the body region extends to a lesser depth from the upper surface of the epitaxial layer than does the trench; and (h) a source region of the first conductivity type formed within an upper portion of the body region and adjacent the trench. The presence of the doped region lying between the bottom portion of the trench and the substrate (also referred to herein as a “trench bottom implant”) serves to reduce the on-resistance of the device.

47. 发明授权

US06627951B2 High speed trench DMOS 有权
标题翻译：高速沟DMOS
公开(公告)号：US06627951B2
公开(公告)日：2003-09-30
申请号：US09882117
申请日：2001-06-15
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/4232 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4916 , H01L29/4925 , H01L29/4933
摘要： A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high frequency applications.
摘要翻译：提供了制造沟槽DMOS的方法，其利用多硅化物和难熔技术来制造出具有低栅极电阻，低栅极电容，降低的分布式RC栅极传播延迟以及用于高频应用的改进的开关速度的沟槽DMOS。

48. 发明授权

US06518152B2 Method of forming a trench schottky rectifier 失效
标题翻译：形成沟槽肖特基整流器的方法
公开(公告)号：US06518152B2
公开(公告)日：2003-02-11
申请号：US10043633
申请日：2002-01-10
申请人： Fwu-Iuan Hshieh , Max Chen , Koon Chong So , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Max Chen , Koon Chong So , Yan Man Tsui
IPC分类号： H01L2128
CPC分类号： H01L29/8725 , H01L29/872
摘要： A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.
摘要翻译：提供肖特基整流器。肖特基整流器包括：（a）具有第一和第二相对面的半导体区域，半导体区域包括邻近第一面的第一导电类型的阴极区域和与第二面相邻的第一导电类型的漂移区域，以及漂移区具有比阴极区更低的净掺杂浓度; （b）从所述第二面延伸到所述半导体区域并限定所述半导体区域内的一个或多个台面的一个或多个沟槽; （c）与沟槽下部的半导体区相邻的绝缘区; （d）和阳极电极（i）在第二面处与半导体相邻并形成肖特基整流接触，（ii）与沟槽上部的半导体区域相邻并形成肖特基整流接触，以及（iii）与沟槽下部的绝缘区域相邻。

49. 发明授权

US06472678B1 Trench MOSFET with double-diffused body profile 有权
标题翻译：具有双扩散体轮廓的沟槽MOSFET
公开(公告)号：US06472678B1
公开(公告)日：2002-10-29
申请号：US09595486
申请日：2000-06-16
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/7811
摘要： A trench MOSFET device and process for making the same are described. The trench MOSFET has a substrate of a first conductivity type, an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate, a plurality of trenches within the epitaxial layer, a first insulating layer, such as an oxide layer, lining the trenches, a conductive region, such as a polycrystalline silicon region, within the trenches adjacent to the first insulating layer, and one or more trench body regions and one or more termination body regions provided within an upper portion of the epitaxial layer, the termination body regions extending into the epitaxial layer to a greater depth than the trench body regions. Each trench body region and each termination body region has a first region of a second conductivity type, the second conductivity type being opposite the first conductivity type, and a second region of the second conductivity type adjacent the first region, the second region having a greater majority carrier concentration than the first region, and the second region being disposed above the first region and adjacent and extending to an outer wall of each of the plurality of trenches. A plurality of source regions of the first conductivity type are positioned adjacent the trenches within upper portions the trench body regions.
摘要翻译：描述了沟槽MOSFET器件及其制造方法。沟槽MOSFET具有第一导电类型的衬底，在衬底上的第一导电类型的外延层，外延层具有比衬底更低的多数载流子浓度，外延层内的多个沟槽，第一绝缘层，诸如沟槽衬里的氧化物层，在与第一绝缘层相邻的沟槽内的导电区域，例如多晶硅区域，以及一个或多个沟槽体区域和设置在上部的一个或多个端接体区域外延层的一部分，终端体区域延伸到外延层中比沟槽体区域更深的深度。每个沟槽体区域和每个终端体区域具有第二导电类型的第一区域，第二导电类型与第一导电类型相反，第二导电类型的第二区域与第一区域相邻，第二区域具有更大的多数载流子浓度比第一区域多，并且第二区域设置在第一区域上方并且相邻并延伸到多个沟槽中的每一个的外壁。第一导电类型的多个源极区域位于沟槽体区域的上部内的沟槽附近。

50. 发明授权

US06426260B1 Switching speed improvement in DMO by implanting lightly doped region under gate 有权
标题翻译：通过在栅极下注入轻掺杂区域，在DMO中切换速度提高
公开(公告)号：US06426260B1
公开(公告)日：2002-07-30
申请号：US09655165
申请日：2000-09-05
申请人： Fwu-Iuan Hshieh
发明人： Fwu-Iuan Hshieh
IPC分类号： H01L21336
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/66712 , H01L29/66734 , H01L29/7813
摘要： The preset invention discloses an improved method for fabricating a MOSFET transistor on a substrate to improve the device ruggedness. The fabrication method includes the steps of: (a) forming an epi-layer of a first conductivity type as a drain region on the substrate and then growing an gate oxide layer over the epi-layer; (b) depositing an overlaying polysilicon layer thereon and applying a polysilicon mask for etching the polysilicon layer to define a plurality of polysilicon gates; (c) removing the polysilicon mask and then carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions; (d) performing a high-energy body-conductivity-type-dopant implant, eg., boron implant, to form a plurality of shallow low-concentration regions of source-conductivity-type, e.g., n-regions, under each of e gates. A DMOS power device with improved switching speed is provided with reduced gate-to-drain capacitance without causing an increase in either the on-resistance of the threshold voltage.
摘要翻译：本发明公开了一种用于在衬底上制造MOSFET晶体管以改善器件耐用性的改进方法。制造方法包括以下步骤：（a）在衬底上形成第一导电类型的外延层作为漏极区域，然后在外延层上生长栅极氧化物层; （b）在其上沉积覆盖多晶硅层并施加多晶硅掩模以蚀刻所述多晶硅层以限定多个多晶硅栅极; （c）去除所述多晶硅掩模，然后执行第二导电类型的体植入物，随后进行用于形成多个体区的体扩散; （d）执行高能量体导电型掺杂剂注入，例如硼注入，以在e的每一个下形成多个源 - 导电型（例如，n区）的浅低浓度区域大门提供了具有改善的开关速度的DMOS功率器件，其具有减小的栅极 - 漏极电容，而不会导致阈值电压的导通电阻的增加。

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