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41. 发明申请

US20110004354A1 METHODS AND APPARATUSES FOR TESTING A SLEEP SUPPORT MEMBER 有权
标题翻译：用于测试休眠支持会员的方法和设备
公开(公告)号：US20110004354A1
公开(公告)日：2011-01-06
申请号：US12867723
申请日：2009-02-13
申请人： Robert D. Oxeman , David B. Scott
发明人： Robert D. Oxeman , David B. Scott
IPC分类号： G05D15/00 , G05D23/00 , G05D7/00
CPC分类号： G01N3/32 , A47C31/123 , G01N2203/0019 , G01N2203/0226 , G01N2203/0246
摘要： Systems and methods for testing a sleep support member. A system including at least one pressing structure, wherein the at least one pressing structure includes at least one of a heater and a moisture device; and a controller configured to control pressing of the pressing structure onto the sleep support member, wherein the controller is configured to control at least one of heat provided by the heater and moisture provided by the moisture device. A method including controlling pressing of at least one pressing structure onto a sleep support member, wherein the at least one pressing structure includes at least one of a heater and a moisture device; and controlling at least one of heat provided by the heater and moisture provided by the moisture device.
摘要翻译：用于测试睡眠支持成员的系统和方法。一种包括至少一个按压结构的系统，其中所述至少一个按压结构包括加热器和湿气装置中的至少一个; 以及控制器，其被配置为控制所述按压结构到所述睡眠支撑构件上的按压，其中所述控制器构造成控制由所述加热器提供的热量和由所述湿气装置提供的湿气中的至少一个。一种方法，包括控制至少一个按压结构到睡眠支撑构件上的按压，其中所述至少一个按压结构包括加热器和湿气装置中的至少一个; 以及控制由加热器提供的热量和由湿气装置提供的湿气中的至少一种。

42. 发明授权

US06620692B2 Method of forming a metal oxide semiconductor transistor with self-aligned channel implant 有权
标题翻译：用自对准沟道植入物形成金属氧化物半导体晶体管的方法
公开(公告)号：US06620692B2
公开(公告)日：2003-09-16
申请号：US10133556
申请日：2002-04-26
申请人： David B. Scott , Dan M. Mosher
发明人： David B. Scott , Dan M. Mosher
IPC分类号： H01L21336
CPC分类号： H01L29/7816 , H01L21/26506 , H01L21/26586 , H01L29/0653 , H01L29/086 , H01L29/42368 , H01L29/66689
摘要： A transistor (50) comprising a gate conductor (68) and a gate insulator (66) separating the gate conductor from a semiconductor material (64) having a first conductivity type. The transistor further comprises a drain region (782) having the first conductivity type. The transistor further comprises an angular implanted region (70) having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge (70a) underlying the gate conductor, and the transistor includes a source region (781) formed at least in part within the angular implanted region. Finally, a transistor channel (74) is defined between an edge (71a) of the source region proximate the gate conductor and the angular implanted region edge (70a) underlying the gate conductor.
摘要翻译：一种晶体管（50），包括将栅极导体与具有第一导电类型的半导体材料（64）分开的栅极导体（68）和栅极绝缘体（66）。晶体管还包括具有第一导电类型的漏区（782）。晶体管还包括具有与第一导电类型互补的第二导电类型并且具有位于栅极导体下方的角度注入区域边缘（70a）的角度注入区域（70），并且晶体管包括至少形成的源极区域（781）部分地在角度注入区域内。最后，晶体管沟道（74）被限定在靠近栅极导体的源极区域的边缘（71a）和栅极导体下面的角度注入区域边缘（70a）之间。

43. 发明授权

US06585328B1 Customized mattress evaluation system 有权
标题翻译：定制床垫评估系统
公开(公告)号：US06585328B1
公开(公告)日：2003-07-01
申请号：US09544958
申请日：2000-04-07
申请人： Robert D. Oexman , David B. Scott
发明人： Robert D. Oexman , David B. Scott
IPC分类号： G06F1900
CPC分类号： G01M99/001 , A47C31/123
摘要： A customized mattress evaluation system allows for uniquely designed mattresses based upon a particular customer's physical attributes. The system allows a retail mattress store to collect data from a sensor pad positioned on top of a support surface to generate a pressure profile for that person. The pressure profile and other information are used to generate specific mattress design parameters or co-efficients which are then utilized in designing a specific mattress uniquely customized for that person. Body type coefficients characteristic of an individual customer are correlated with coefficients developed for test persons for which various bedding products have been optimized. The optimization includes the rating of various bedding products for various body types by minimizing support pressures across the mattress and optimizing lumbar support for desired spinal curvature.
摘要翻译：定制的床垫评估系统允许基于特定客户的物理属性设计独特的床垫。该系统允许零售床垫商店从位于支撑表面顶部的传感器垫收集数据，以产生该人的压力分布。压力分布和其他信息用于产生特定的床垫设计参数或系数，然后用于设计为该人独特定制的特定床垫。个体客户的身体类型系数特征与为各种床上用品已被优化的测试人员开发的系数相关联。优化包括通过最小化床垫上的支撑压力并优化腰椎支撑以达到理想的脊柱弯曲的各种身体类型的各种床上用品的等级。

44. 发明授权

US06202511B1 Vibration damped hammer 有权
标题翻译：振动减震锤
公开(公告)号：US06202511B1
公开(公告)日：2001-03-20
申请号：US09371586
申请日：1999-08-10
申请人： John C. Murray , David B. Scott
发明人： John C. Murray , David B. Scott
IPC分类号： B25D100
CPC分类号： B25G1/01
摘要： A hammer includes a rigid elongated support structure, a head carried at one end of the support structure, and a manually engageable gripping portion. An end of the elongated support structure includes a pair of vibration-receiving portions terminating in spaced apart relation with respect to each other and spaced from each other in a direction parallel to a swing plane of the hammer. The manually engageable gripping portion is formed from a resiliently deformable material molded around a portion of the support structure including the vibration-receiving portions so as to fill the space between the vibration-receiving portions. Vibration forces acting in a direction parallel to the swing plane of the hammer are generated by striking a striking surface of the head against an object. A portion of the vibration energy is transmitted through the support structure to the vibration-receiving portions, where the vibration energy is dampened and thereby dissipated by the resiliently deformable material surrounding the vibration-receiving portions. Accordingly, the level of vibration transmitted to the hand of the user is reduced.
摘要翻译：锤包括刚性细长支撑结构，在支撑结构的一端承载的头部和可手动接合的夹持部分。细长支撑结构的一端包括一对振动接收部分，它们以相互间隔开的关系终止并且在平行于锤的摆动平面的方向上彼此间隔开。可手动接合的抓握部分由围绕包括振动接收部分的支撑结构的一部分模制的可弹性变形材料形成，以便填充振动接收部分之间的空间。通过将头部的击打表面撞击物体来产生沿与锤的摆动平面平行的方向作用的振动力。振动能量的一部分通过支撑结构传递到振动接收部分，其中振动能量被衰减，从而由围绕振动接收部分的弹性变形材料消散。因此，减少了传递给用户的手的振动水平。

45. 发明授权

US5291444A Combination DRAM and SRAM memory array 失效
标题翻译：组合DRAM和SRAM存储器阵列
公开(公告)号：US5291444A
公开(公告)日：1994-03-01
申请号：US812676
申请日：1991-12-23
申请人： David B. Scott , Hiep Van Tran
发明人： David B. Scott , Hiep Van Tran
IPC分类号： G11C11/403 , G11C7/10 , G11C11/00 , G11C11/409 , G11C11/4096 , G11C11/412 , G11C7/00
CPC分类号： G11C7/106 , G11C11/005 , G11C11/4096 , G11C7/1051 , G11C7/1078 , G11C2207/108
摘要： A combination dynamic random access memory (DRAM) and static random access memory (SRAM) (150) array, includes a plurality of DRAM sense amplifiers (82, 84), each coupled to at least one DRAM bitline (86), with a plurality of DRAM memory cells selectively coupled to each of the bitlines (86). The sense amplifiers (82, 84) are organized into groups, with each group of sense amplifiers (82, 84), selectively coupled to respective true and complement I/O lines (102, 104). For each pair of the true and complement I/O lines (102, 104), an SRAM latch (150) is coupled to the pair.
摘要翻译：组合动态随机存取存储器（DRAM）和静态随机存取存储器（SRAM）（150）阵列包括多个DRAM读出放大器（82,84），每个DRAM读出放大器耦合到至少一个DRAM位线（86），具有多个选择性地耦合到每个位线（86）的DRAM存储单元。感测放大器（82,84）被组织成组，每组读出放大器（82,84）选择性地耦合到相应的真和补充I / O线（102,104）。对于每对真实和补充I / O线（102,104），SRAM锁存器（150）耦合到该对。

46. 发明授权

US5070381A High voltage lateral transistor 失效
标题翻译：高压横向晶体管
公开(公告)号：US5070381A
公开(公告)日：1991-12-03
申请号：US496487
申请日：1990-03-20
申请人： David B. Scott , Hiep V. Tran
发明人： David B. Scott , Hiep V. Tran
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/8224 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/73 , H01L29/732 , H01L29/735
CPC分类号： H01L29/6625 , H01L21/8224 , H01L21/8249 , H01L29/735
摘要： The described embodiments of the present invention provide a structure and method for easily incorporating a high voltage lateral bipolar transistor in an integrated circuit. A buried base contact is formed and the base itself is formed of a well region in the integrated circuit. An oppositely doped well region is formed surrounding the collector region in the lateral PNP transistor. This collector well is formed of the opposite conductivity type of the base well. Contact to the collector and a heavily doped emitter are then formed in the collector well and base well, respectively. The more lightly doped collector well provides a thick depletion region between the collector and base and thus provides higher voltage operation. The positioning of the base/collector junction to the collector well at base well junction also reduces the spacing between the collector and the emitter. This reduced spacing provides greater carrier injection from the forward biased base/emitter junction to the reverse biased base/collector junction. Thus, the performance of the lateral PNP transistor is improved. This structure is easily incorporated with standard BiCMOS processing and may be incorporated with other bipolar processing.
摘要翻译：本发明的所述实施例提供了一种用于在集成电路中容易地并入高压侧向双极晶体管的结构和方法。形成掩埋的基极接触，并且基底本身由集成电路中的阱区形成。围绕横向PNP晶体管中的集电极区域形成相对掺杂的阱区。该收集阱由相对导电类型的基础井形成。然后分别在收集器阱和基极中形成与集电极和重掺杂发射极的接触。较轻掺杂的集电极阱在集电极和基极之间提供了一个较厚的耗尽区，从而提供更高的电压操作。基极/集电极结到基极阱接合处的集电极阱的定位也减小了集电极和发射极之间的间距。该减小的间隔提供从正向偏置的基极/发射极结到反向偏置的基极/集电极结的更大的载流子注入。因此，提高了横向PNP晶体管的性能。该结构容易地与标准的BiCMOS处理结合，并且可以与另外的双极性处理相结合。

47. 发明授权

US4984196A High performance bipolar differential sense amplifier in a BiCMOS SRAM 失效
标题翻译： BiCMOS SRAM中的高性能双极差分读出放大器
公开(公告)号：US4984196A
公开(公告)日：1991-01-08
申请号：US198368
申请日：1988-05-25
申请人： Hiep V. Tran , David B. Scott
发明人： Hiep V. Tran , David B. Scott
IPC分类号： G11C7/06 , G11C11/415 , G11C11/416 , G11C11/418 , G11C11/419 , H01L27/10 , H01L27/102
CPC分类号： G11C7/062 , G11C11/415 , G11C11/416 , G11C11/418 , G11C11/419 , H01L27/1025
摘要： A sensing and decoding scheme layout for a memory device comprising an array made up of columns and rows of memory cells is disclosed wherein sense amplifiers and pairs of memory cell columns are positioned so as to collectively fit within the pitches of the memory cells of the memory cell column pairs and where the sense amplifiers are connected in a one-to-one correspondence with columns of the memory cells.
摘要翻译：公开了一种用于存储器件的感测和解码方案布局，其包括由列和行的存储器单元组成的阵列，其中读出放大器和存储单元列对被定位成共同装配在存储器的存储器单元的间距内单元列对，并且其中读出放大器与存储器单元的列一一对应地连接。

48. 发明授权

US4476482A Silicide contacts for CMOS devices 失效
标题翻译： CMOS器件的硅化物触点
公开(公告)号：US4476482A
公开(公告)日：1984-10-09
申请号：US377759
申请日：1982-05-13
申请人： David B. Scott , Roderick D. Davies , Yee-Chaung See
发明人： David B. Scott , Roderick D. Davies , Yee-Chaung See
IPC分类号： H01L21/285 , H01L21/60 , H01L27/092 , H01L23/48 , H01L29/04 , H01L29/46 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/28518 , H01L21/76895 , H01L27/0928
摘要： In the manufacture of a CMOS device, oxide is etched away from polysilicon gate-level interconnects, and from source or drain regions of either conductivity type to which the polysilicon gate-level interconnect is desired to be connected. A metal is then deposited, and silicide is formed to connect the gate-level interconnect to the respective source and drain regions. To ensure continuity of the silicide connection, the gate oxide beneath the gate level interconnect is slightly undercut by a wet etching process, additional polysilicon is deposited conformally overall, and the additional polysilicon is anisotropically etched so that it is removed from all areas except those within the undercut region beneath the gate-level interconnect thus a continuous surface of silicon, from which a continuous layer of silicide is then grown, exists between the polysilicon gate-level interconnect and the respective source and drain regions. Thus, self-aligned contacts are created, and no unwanted pn junctions are created.
摘要翻译：在CMOS器件的制造中，氧化物被蚀刻掉离开多晶硅栅极级互连，并且需要与要连接多晶硅栅极级互连的导电类型的源极或漏极区域。然后沉积金属，并且形成硅化物以将栅极级互连件连接到相应的源极和漏极区域。为了确保硅化物连接的连续性，栅极级互连下方的栅极氧化物通过湿式蚀刻工艺略微下切，另外的多晶硅整体平坦地沉积，并且附加的多晶硅被各向异性地蚀刻，使得其从除了栅极级互连之下的底切区域因此存在于多晶硅栅极级互连件和相应的源极和漏极区域之间的硅的连续表面，硅的连续表面从中生长连续的硅化物层。因此，产生自对准的触点，并且不产生不需要的pn结。

49. 发明授权

US4374700A Method of manufacturing silicide contacts for CMOS devices 失效
标题翻译：制造CMOS器件硅化物触点的方法
公开(公告)号：US4374700A
公开(公告)日：1983-02-22
申请号：US268201
申请日：1981-05-29
申请人： David B. Scott , Roderick D. Davies , Yee-Chaung See
发明人： David B. Scott , Roderick D. Davies , Yee-Chaung See
IPC分类号： H01L27/092 , H01L21/285 , H01L21/768 , H01L21/8238 , H01L29/78 , H01L21/308 , H01L21/24 , H01L21/283
CPC分类号： H01L21/823814 , H01L21/28518 , H01L21/76889 , H01L21/76895 , H01L27/0928
摘要： In the manufacture of a CMOS device, oxide is etched away from polysilicon gate-level interconnects, and from source or drain regions of either conductivity type to which the polysilicon gate-level interconnect is desired to be connected. A metal is then deposited, and silicide is formed to connect the gate-level interconnect to the respective source and drain regions. To ensure continuity of the silicide connection, the gate oxide beneath the gate level interconnect is slightly undercut by a wet etching process, additional polysilicon is deposited conformally overall, and the additional polysilicon is anistropically etched so that it is removed from all areas except those within the undercut region beneath the gate-level interconnect thus a continuous surface of silicon, from which a continuous layer of silicide is then grown, exists between the polysilicon gate-level interconnect and the respective source and drain regions. Thus, self-aligned contacts are created, and no unwanted pn junctions are created.
摘要翻译：在CMOS器件的制造中，氧化物被蚀刻掉离开多晶硅栅极级互连，并且需要与要连接多晶硅栅极级互连的导电类型的源极或漏极区域。然后沉积金属，并且形成硅化物以将栅极级互连件连接到相应的源极和漏极区域。为了确保硅化物连接的连续性，栅极级互连下方的栅极氧化物通过湿蚀刻工艺略微削弱，另外的多晶硅整体平坦地沉积，并且附加多晶硅被静电蚀刻，使得其从除了栅极级互连之下的底切区域因此存在于多晶硅栅极级互连件和相应的源极和漏极区域之间的硅的连续表面，硅的连续表面从中生长连续的硅化物层。因此，产生自对准的触点，并且不产生不需要的pn结。

50. 发明授权

US08770020B2 Methods and apparatuses for testing a sleep support member 有权
标题翻译：用于测试睡眠支持构件的方法和装置
公开(公告)号：US08770020B2
公开(公告)日：2014-07-08
申请号：US12867723
申请日：2009-02-13
申请人： Robert D. Oexman , David B. Scott
发明人： Robert D. Oexman , David B. Scott
IPC分类号： A61B5/103
CPC分类号： G01N3/32 , A47C31/123 , G01N2203/0019 , G01N2203/0226 , G01N2203/0246
摘要： Systems and methods for testing a sleep support member. A system including at least one pressing structure, wherein the at least one pressing structure includes at least one of a heater and a moisture device; and a controller configured to control pressing of the pressing structure onto the sleep support member, wherein the controller is configured to control at least one of heat provided by the heater and moisture provided by the moisture device. A method including controlling pressing of at least one pressing structure onto a sleep support member, wherein the at least one pressing structure includes at least one of a heater and a moisture device; and controlling at least one of heat provided by the heater and moisture provided by the moisture device.
摘要翻译：用于测试睡眠支持成员的系统和方法。一种包括至少一个按压结构的系统，其中所述至少一个按压结构包括加热器和湿气装置中的至少一个; 以及控制器，其被配置为控制所述按压结构到所述睡眠支撑构件上的按压，其中所述控制器构造成控制由所述加热器提供的热量和由所述湿气装置提供的湿气中的至少一个。一种方法，包括控制至少一个按压结构到睡眠支撑构件上的按压，其中所述至少一个按压结构包括加热器和湿气装置中的至少一个; 以及控制由加热器提供的热量和由湿气装置提供的湿气中的至少一种。

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