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    • 47. 发明授权
    • Method for detecting the locking of a phase-locked loop and associated device
    • 用于检测锁相环和相关装置的锁定的方法
    • US08212597B2
    • 2012-07-03
    • US12688098
    • 2010-01-15
    • Michael KraemerSébastien Rieubon
    • Michael KraemerSébastien Rieubon
    • H03L7/06
    • H04L7/0331H03L7/095H04L7/033
    • A method is for detecting locking of a phase-locked loop that generates an output signal and includes a phase comparator receiving, as an input, a reference signal and a second signal based upon the output signal. A time window having a duration of at least two periods of a third signal based upon the output signal, and located about a payload edge of the second signal, is generated. A first comparison of the reference signal and the second signal at a first payload edge of the third signal within the time window and on a first side of the payload edge of the second signal is performed. A second comparison of the reference signal and the second signal at a second payload edge of the third signal within the time window and on a second side of the payload edge of the second signal is then performed. Locking of the phase-locked loop based upon the reference signal and the second signal being equal during the first and second comparisons is detected.
    • 一种用于检测产生输出信号的锁相环的锁定的方法,包括基于输出信号作为输入接收参考信号和第二信号的相位比较器。 产生具有基于输出信号的第三信号的至少两个周期的持续时间并且位于第二信号的有效负载边缘周围的时间窗口。 执行在第二信号的有效载荷边缘的时间窗内和第一侧的第三信号的第一有效载荷边缘处的参考信号和第二信号的第一比较。 然后,执行第二信号的有效载荷边缘的时间窗内和第二侧的第三信号的第二有效载荷边缘处的参考信号和第二信号的第二比较。 检测在第一和第二比较期间基于参考信号和第二信号相等的锁相环的锁定。
    • 50. 发明授权
    • Counter with correction circuitry
    • 带校正电路的计数器
    • US07466789B2
    • 2008-12-16
    • US11724517
    • 2007-03-15
    • Sébastien RieubonMichael Kraemer
    • Sébastien RieubonMichael Kraemer
    • H03K25/00H03K9/06H03D3/00
    • H03K21/406
    • The invention concerns counting circuitry for providing a corrected count value based on the number of rising and falling edges of an input signal occurring during a reference time period, the counting circuitry comprising a counter (22) arranged to provide a first count value based on one of the number of said rising edges of said input signal occurring during said reference time period, and the number of said falling edges of said input signal occurring during said reference time period; characterized in that said counting circuitry further comprises adjustment circuitry (24-26) arranged to generate a corrected count value by determining the state of said input signal at the start time (70) and end time (72) of said reference time period, and adjusting said first count value if the state of said input signal at the start of said reference time period is different from the state of said input signal at the end of said reference time period.
    • 本发明涉及用于基于在参考时间段期间发生的输入信号的上升沿和下降沿的数量来提供经校正的计数值的计数电路,该计数电路包括一个计数器,该计数器被布置为基于数字中的一个提供第一计数值 在参考时间段期间发生的输入信号的上升沿和在参考时间段期间发生的输入信号的下降沿的数量; 其中所述计数电路还包括调整电路,所述调整电路被布置成通过在所述参考时间段的开始时间和结束时间确定所述输入信号的状态来产生校正的计数值,以及如果所述输入信号的状态在 参考时间段的开始与参考时间段结束时的输入信号的状态不同。