专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US08026539B2 Metal oxide semiconductor devices having doped silicon-compromising capping layers and methods for fabricating the same 有权
标题翻译：具有掺杂的含硅覆盖层的金属氧化物半导体器件及其制造方法
公开(公告)号：US08026539B2
公开(公告)日：2011-09-27
申请号：US12388094
申请日：2009-02-18
申请人： Michael Hargrove , Frank Bin Yang , Rohit Pal
发明人： Michael Hargrove , Frank Bin Yang , Rohit Pal
IPC分类号： H01L29/76
CPC分类号： H01L21/28088 , H01L21/28079 , H01L21/823842 , H01L21/82385 , H01L29/1054 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.
摘要翻译：提供了用于形成包括半导体衬底的半导体器件的方法。根据示例性实施例，一种方法包括以下步骤：形成覆盖在半导体衬底上的高k电介质层，形成覆盖在高k电介质层上的包含金属的栅极层，形成掺杂的含硅覆盖层含金属的栅极层，以及沉积覆盖掺杂的含硅覆盖层的含硅栅极层。

42. 发明申请

US20100295103A1 GATE ETCH OPTIMIZATION THROUGH SILICON DOPANT PROFILE CHANGE 有权
标题翻译：通过硅掺杂物轮廓变化进行GATE蚀刻优化
公开(公告)号：US20100295103A1
公开(公告)日：2010-11-25
申请号：US12469418
申请日：2009-05-20
申请人： Man Fai Ng , Rohit Pal
发明人： Man Fai Ng , Rohit Pal
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/32155 , H01L21/322 , H01L29/7833
摘要： Improved semiconductor devices comprising metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.
摘要翻译：通过降低覆盖在金属层上的硅层顶部的初始高掺杂剂浓度，形成包括金属栅电极的改进的半导体器件，具有降低的性能可变性。实施例包括通过将反掺杂剂注入硅层的上部来去除高掺杂剂浓度部分并用未掺杂的或轻掺杂的硅代替它来减少硅层上部的掺杂剂浓度，并施加吸气剂到硅层的上表面以形成具有吸收的掺杂剂的薄层，该层可以被去除或保留。

43. 发明申请

US20100289089A1 ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A GATE DIELECTRIC CAP LAYER MATERIAL PRIOR TO GATE DIELECTRIC STABILIZATION 有权
标题翻译：通过扩大栅极电介质层材料来调节放电晶体管的栅极电压以进行电介质稳定化
公开(公告)号：US20100289089A1
公开(公告)日：2010-11-18
申请号：US12775555
申请日：2010-05-07
申请人： Richard Carter , Martin Trentzsch , Sven Beyer , Rohit Pal
发明人： Richard Carter , Martin Trentzsch , Sven Beyer , Rohit Pal
IPC分类号： H01L27/088 , H01L21/28 , H01L21/20 , H01L21/336
CPC分类号： H01L21/823462 , H01L21/28176 , H01L21/28194 , H01L29/513 , H01L29/517
摘要： Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies.
摘要翻译：复杂的栅极电极结构可以通过在进行用于稳定敏感栅极介电材料的处理之前提供包括可能扩散到栅极电介质材料中的所需物质的覆盖层来形成。以这种方式，与常规策略相比，可以基于用于阈值调节物质的降低的温度和剂量来形成复杂的高k金属栅电极结构。

44. 发明申请

US20100207176A1 Metal oxide semiconductor devices having doped silicon-compromising capping layers and methods for fabricating the same 有权
标题翻译：具有掺杂的含硅覆盖层的金属氧化物半导体器件及其制造方法
公开(公告)号：US20100207176A1
公开(公告)日：2010-08-19
申请号：US12388094
申请日：2009-02-18
申请人： Michael Hargrove , Frank Bin Yang , Rohit Pal
发明人： Michael Hargrove , Frank Bin Yang , Rohit Pal
IPC分类号： H01L29/78 , H01L21/4763
CPC分类号： H01L21/28088 , H01L21/28079 , H01L21/823842 , H01L21/82385 , H01L29/1054 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.
摘要翻译：提供了用于形成包括半导体衬底的半导体器件的方法。根据示例性实施例，一种方法包括以下步骤：形成覆盖在半导体衬底上的高k电介质层，形成覆盖在高k电介质层上的包含金属的栅极层，形成掺杂的含硅覆盖层含金属的栅极层，以及沉积覆盖掺杂的含硅覆盖层的含硅栅极层。

45. 发明授权

US07704840B2 Stress enhanced transistor and methods for its fabrication 有权
标题翻译：应力增强晶体管及其制造方法
公开(公告)号：US07704840B2
公开(公告)日：2010-04-27
申请号：US11611784
申请日：2006-12-15
申请人： Igor Peidous , Rohit Pal
发明人： Igor Peidous , Rohit Pal
IPC分类号： H01L21/336
CPC分类号： H01L29/78687 , H01L29/66553 , H01L29/66621 , H01L29/66628 , H01L29/66772 , H01L29/7848
摘要： A stress enhanced MOS transistor and methods for its fabrication are provided. A semiconductor-on-insulator structure is provided which includes a semiconductor layer having a first surface. A strain-inducing epitaxial layer is blanket deposited over the first surface, and can then be used to create a source region and a drain region which overlie the first surface.
摘要翻译：提供了一种应力增强型MOS晶体管及其制造方法。提供了一种绝缘体上半导体结构，其包括具有第一表面的半导体层。应变诱导外延层被覆盖地沉积在第一表面上，然后可用于产生覆盖在第一表面上的源极区域和漏极区域。

46. 发明授权

US07632727B2 Method of forming stepped recesses for embedded strain elements in a semiconductor device 有权
标题翻译：在半导体器件中形成用于嵌入式应变元件的阶梯式凹陷的方法
公开(公告)号：US07632727B2
公开(公告)日：2009-12-15
申请号：US12119384
申请日：2008-05-12
申请人： Rohit Pal , Frank Bin Yang , Michael Hargrove
发明人： Rohit Pal , Frank Bin Yang , Michael Hargrove
IPC分类号： H01L29/772
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/26586 , H01L21/3065 , H01L29/165 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A method of fabricating a semiconductor transistor device is provided. The fabrication method begins by forming a gate structure overlying a layer of semiconductor material, such as silicon. Then, spacers are formed about the sidewalls of the gate structure. Next, ions of an amorphizing species are implanted into the semiconductor material at a tilted angle toward the gate structure. The gate structure and the spacers are used as an ion implantation mask during this step. The ions form amorphized regions in the semiconductor material. Thereafter, the amorphized regions are selectively removed, resulting in corresponding recesses in the semiconductor material. In addition, the recesses are filled with stress inducing semiconductor material, and fabrication of the semiconductor transistor device is completed.
摘要翻译：提供一种制造半导体晶体管器件的方法。制造方法通过形成覆盖诸如硅的半导体材料层的栅极结构开始。然后，围绕栅极结构的侧壁形成间隔物。接下来，非晶化物质的离子以倾斜的角度注入到栅极结构中。在该步骤中，栅极结构和间隔物用作离子注入掩模。离子在半导体材料中形成非晶化区域。此后，非晶化区域被选择性地去除，从而在半导体材料中产生相应的凹槽。此外，凹部被应力诱导半导体材料填充，并且半导体晶体管器件的制造完成。

47. 发明申请

US20080248598A1 METHOD AND APPARATUS FOR DETERMINING CHARACTERISTICS OF A STRESSED MATERIAL USING SCATTEROMETRY 审中-公开
标题翻译：用于确定应力分布特征的材料的方法和装置
公开(公告)号：US20080248598A1
公开(公告)日：2008-10-09
申请号：US11697955
申请日：2007-04-09
申请人： Rohit Pal , Alok Vaid
发明人： Rohit Pal , Alok Vaid
IPC分类号： H01L21/66 , H01L21/306 , H01L23/58
CPC分类号： H01L22/12
摘要： A method includes illuminating at least a portion of a first grid including a first plurality of stressed material regions formed at least partially in a semiconducting material. Light reflected from the illuminated portion of the first grid is measured to generate a first reflection profile. A characteristic of the first plurality of stressed material regions is determined based on the first reflection profile. A test structure includes a first plurality of stressed material regions recessed with respect to a surface of a semiconductor layer and defining a first grid. A first plurality of exposed portions of the semiconductor layer is disposed between each of the first plurality of stressed material regions.
摘要翻译：一种方法包括照亮包括至少部分地形成在半导体材料中的第一多个应力材料区域的第一栅格的至少一部分。测量从第一格栅的照明部分反射的光以产生第一反射曲线。基于第一反射曲线确定第一多个应力材料区域的特性。测试结构包括相对于半导体层的表面凹陷并限定第一格栅的第一多个应力材料区域。半导体层的第一多个暴露部分设置在第一多个应力材料区域中的每一个之间。

48. 发明授权

US08525289B2 Adjusting threshold voltage for sophisticated transistors by diffusing a gate dielectric cap layer material prior to gate dielectric stabilization 有权
标题翻译：通过在栅极电介质稳定之前扩散栅介质盖层材料来调整复杂晶体管的阈值电压
公开(公告)号：US08525289B2
公开(公告)日：2013-09-03
申请号：US13444955
申请日：2012-04-12
申请人： Richard Carter , Martin Trentzsch , Sven Beyer , Rohit Pal
发明人： Richard Carter , Martin Trentzsch , Sven Beyer , Rohit Pal
IPC分类号： H01L23/58
CPC分类号： H01L21/823462 , H01L21/28176 , H01L21/28194 , H01L29/513 , H01L29/517
摘要： Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.
摘要翻译：复杂的栅极电极结构可以通过在进行用于稳定敏感栅极介电材料的处理之前提供包括可能扩散到栅极电介质材料中的所需物质的覆盖层来形成。以这种方式，与常规策略相比，可以基于用于阈值调节物质的降低的温度和剂量来形成复杂的高k金属栅电极结构。此外，可以为两种类型的晶体管沉积单个含金属的电极材料。

49. 发明授权

US08445964B2 Fabrication of semiconductors with high-K/metal gate electrodes 有权
标题翻译：具有高K /金属栅电极的半导体制造
公开(公告)号：US08445964B2
公开(公告)日：2013-05-21
申请号：US13349883
申请日：2012-01-13
申请人： Rohit Pal , Stephan Waidmann
发明人： Rohit Pal , Stephan Waidmann
IPC分类号： H01L21/02
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L21/84 , H01L27/1203 , H01L29/6653 , H01L29/6656 , H01L29/78
摘要： Semiconductor devices with high-K/metal gates are formed with spacers that are substantially resistant to subsequent etching to remove an overlying spacer, thereby avoiding replacement and increasing manufacturing throughput. Embodiments include forming a high-K/metal gate, having an upper surface and side surfaces, over a substrate, e.g., a SOI substrate, and sequentially forming, on the side surfaces of the high-K/metal gate, a first spacer of a non-oxide material, a second spacer, of a material different from that of the first spacer, and a third spacer, of a material different from that of the second spacer. After formation of source and drain regions, e.g., epitaxially grown silicon-germanium, the third spacer is etched with an etchant, such as hot phosphoric acid, to which the second spacer is substantially resistant, thereby avoiding replacement.
摘要翻译：具有高K /金属栅极的半导体器件由间隔物形成，其具有基本上抵抗后续蚀刻以去除上覆间隔物，从而避免替换并增加制造生产量。实施例包括在衬底（例如SOI衬底）上形成具有上表面和侧表面的高K /金属栅极，并且在高K /金属栅极的侧表面上依次形成第一间隔物不同于第一间隔物的材料的非氧化物材料，第二间隔物和与第二间隔物不同的材料的第三间隔物。在形成源极和漏极区域，例如外延生长的硅 - 锗之后，用蚀刻剂（例如热磷酸）蚀刻第三间隔物，第二间隔物基本上抵抗其上，从而避免更换。

50. 发明申请

US20130034942A1 HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY EARLY CAP LAYER ADAPTATION 有权
标题翻译：高K金属电极结构由早期盖层适应形成
公开(公告)号：US20130034942A1
公开(公告)日：2013-02-07
申请号：US13565970
申请日：2012-08-03
申请人： Rohit Pal , Sven Beyer , Andy Wei , Richard Carter
发明人： Rohit Pal , Sven Beyer , Andy Wei , Richard Carter
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828
摘要： When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.
摘要翻译：当在不同导电类型的晶体管中形成高k金属栅极电极结构时，同时在一种类型的晶体管中选择性地并入嵌入式应变诱导半导体合金，可以通过选择性地减小介电帽材料的厚度来实现优异的工艺均匀性栅极层堆叠在不接收应变诱导半导体合金的晶体管的有源区上方。在这种情况下，可以在早期制造阶段中形成复杂的高k金属栅极电极结构的工艺策略中实现优异的限制和因此敏感栅极材料的完整性，而在替代栅极方法中，优良的工艺均匀性是在暴露观察者电极材料的表面时实现。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式