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    • 47. 发明申请
    • Group 3B nitride crystal
    • 3B族氮化物晶体
    • US20110287222A1
    • 2011-11-24
    • US13136056
    • 2011-07-21
    • Takayuki HiraoMakoto IwaiKatsuhiro Imai
    • Takayuki HiraoMakoto IwaiKatsuhiro Imai
    • C01B21/06B32B3/00
    • C30B29/403C30B9/10C30B29/406Y10T428/24355
    • A sapphire substrate on a surface of which a thin film of gallium nitride is formed is prepared as a seed-crystal substrate and placed in a growth vessel. Gallium and sodium metals are weighed to achieve a molar ratio of 25 to 32:68 to 75 and added into the vessel. The vessel is put into a reaction vessel. An inlet pipe is connected to the reaction vessel. Nitrogen gas is introduced from a nitrogen tank through a pressure controller to fill the reaction vessel. While the internal pressure of the reaction vessel is controlled to be a predetermined nitrogen gas pressure and target temperatures are set such that the temperature of a lower heater is higher than the temperature of an upper heater, a gallium nitride crystal is grown. As a result, a group 13 nitride crystal having a large grain size and a low dislocation density is provided.
    • 制备其上形成有氮化镓薄膜的表面上的蓝宝石衬底作为晶种衬底并置于生长容器中。 称量镓和钠金属以达到25至32:68至75的摩尔比并加入容器中。 将容器放入反应容器中。 入口管连接到反应容器。 从氮气罐通过压力控制器引入氮气以填充反应容器。 当将反应容器的内部压力控制为预定的氮气压力并且设定目标温度使得下部加热器的温度高于上部加热器的温度时,生长氮化镓晶体。 结果,提供了具有大晶粒尺寸和低位错密度的13族氮化物晶体。
    • 49. 发明授权
    • Nonvolatile semiconductor memory
    • 非易失性半导体存储器
    • US08223543B2
    • 2012-07-17
    • US13193968
    • 2011-07-29
    • Makoto IwaiHiroshi Nakamura
    • Makoto IwaiHiroshi Nakamura
    • G11C16/04
    • G11C16/3459G11C11/56G11C11/5628G11C11/5635G11C11/5642G11C16/0483G11C16/06G11C16/08G11C16/26G11C16/3436G11C16/3454
    • A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
    • 存储器包括第一和第二选择栅极晶体管,存储器单元,源极线,位线,连接到作为验证读取的目标的所选存储单元的选定字线,连接的未选择字线 到除所选存储单元之外的未选择的存储单元,用于产生提供给所选择的字线的所选择的读取电位并产生大于所选择的读取电位的未被选择的读取电位的电位产生电路, 以及控制电路,其通过验证被选择的存储器单元的单元电流属于两个值隔离的三个区域中的哪个区域属于三个组中的一个,将选择的存储单元的阈值电压分类为三个组中的一个 当所选择的读取电位为第一值时。
    • 50. 发明申请
    • NONVOLATILE SEMICONDUCTOR MEMORY, METHOD FOR READING OUT THEREOF, AND MEMORY CARD
    • 非易失性半导体存储器,其读出方法和存储卡
    • US20110299339A1
    • 2011-12-08
    • US13210431
    • 2011-08-16
    • Makoto IwaiYoshihisa Watanabe
    • Makoto IwaiYoshihisa Watanabe
    • G11C16/26
    • G11C16/0483G11C11/5642G11C16/26
    • A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.
    • 非易失性半导体存储器包括:存储单元单元,包括具有电荷累积层和控制电极的多个存储单元,所述存储单元串联电连接; 多个字线,其各自电连接到所述多个存储单元的所述控制电极; 在所述存储单元单元的一端电连接到所述存储单元的源极线; 在所述存储单元单元的另一端电连接到所述存储单元的位线; 以及控制信号生成电路,其在数据读出操作期间,从连接到未选择的存储器的未选择的字线的选择时刻开始,选择连接到所述存储单元的所述存储单元的字线的定时。