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41. 发明授权

US07493229B2 Adjusting voltage for a phase locked loop based on temperature 失效
标题翻译：基于温度调节锁相环的电压
公开(公告)号：US07493229B2
公开(公告)日：2009-02-17
申请号：US11780498
申请日：2007-07-20
申请人： David W. Boerstler , Nathaniel R. Chadwick , Eskinder Hailu , Kirk D. Peterson , Jieming Qi
发明人： David W. Boerstler , Nathaniel R. Chadwick , Eskinder Hailu , Kirk D. Peterson , Jieming Qi
IPC分类号： G01K3/00 , G06F15/00
CPC分类号： H03L1/022 , H03L1/026 , H03L7/0995
摘要： A mechanism for utilizing a single set of one or more thermal sensors, e.g., thermal diodes, provided on the integrated circuit device, chip, etc., to control the operation of the integrated circuit device, associated cooling system, and high-frequency PLLs is provided. By utilizing a single set of thermal sensors to provide multiple functions, e.g., controlling the operation of the integrated circuit device, the cooling system, and the PLLs, silicon real-estate usage is reduced through combining circuitry functionality. Moreover, the integrated circuit device yield is improved by reducing circuitry complexity and increasing PLL robustness to temperature. Furthermore, the PLL circuitry operating range is improved by compensating for temperature.
摘要翻译：一种用于利用设置在集成电路器件，芯片等上的单组一个或多个热传感器（例如热二极管）来控制集成电路器件，相关冷却系统和高频PLL的操作的机构被提供。通过利用单组热传感器来提供多种功能，例如控制集成电路器件，冷却系统和PLL的操作，通过组合电路功能降低硅的不动产使用。此外，通过降低电路复杂度并增加PLL对于温度的鲁棒性，可以提高集成电路器件的产量。此外，通过补偿温度来提高PLL电路的工作范围。

42. 发明申请

US20090024349A1 ADJUSTING VOLTAGE FOR A PHASE LOCKED LOOP BASED ON TEMPERATURE 失效
标题翻译：基于温度调节相位锁定环路的电压
公开(公告)号：US20090024349A1
公开(公告)日：2009-01-22
申请号：US11780498
申请日：2007-07-20
申请人： David W. Boerstler , Nathaniel R. Chadwick , Eskinder Hailu , Kirk D. Peterson , Jieming Qi
发明人： David W. Boerstler , Nathaniel R. Chadwick , Eskinder Hailu , Kirk D. Peterson , Jieming Qi
IPC分类号： G06F15/00 , H03L1/02
CPC分类号： H03L1/022 , H03L1/026 , H03L7/0995
摘要： A mechanism for utilizing a single set of one or more thermal sensors, e.g., thermal diodes, provided on the integrated circuit device, chip, etc., to control the operation of the integrated circuit device, associated cooling system, and high-frequency PLLs is provided. By utilizing a single set of thermal sensors to provide multiple functions, e.g., controlling the operation of the integrated circuit device, the cooling system, and the PLLs, silicon real-estate usage is reduced through combining circuitry functionality. Moreover, the integrated circuit device yield is improved by reducing circuitry complexity and increasing PLL robustness to temperature. Furthermore, the PLL circuitry operating range is improved by compensating for temperature.
摘要翻译：一种用于利用设置在集成电路器件，芯片等上的单组一个或多个热传感器（例如热二极管）来控制集成电路器件，相关冷却系统和高频PLL的操作的机构被提供。通过利用单组热传感器来提供多种功能，例如控制集成电路器件，冷却系统和PLL的操作，通过组合电路功能降低硅的不动产使用。此外，通过降低电路复杂度并增加PLL对于温度的鲁棒性，可以提高集成电路器件的产量。此外，通过补偿温度来提高PLL电路的工作范围。

43. 发明申请

US20090007047A1 Design Structure for a Phase Locked Loop with Stabilized Dynamic Response 有权
标题翻译：具有稳定动态响应的锁相环的设计结构
公开(公告)号：US20090007047A1
公开(公告)日：2009-01-01
申请号：US12128678
申请日：2008-05-29
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F17/50 , H03L7/085
CPC分类号： H03L7/099 , H03L7/093 , H03L7/183 , H03L2207/04
摘要： A design structure for a hybrid phase locked loop (PLL) circuit that obtains stabilized dynamic response and independent adjustment of damping factor and loop bandwidth is provided. The hybrid PLL circuit of the illustrative embodiments includes the resistance/capacitance (RC) filter elements of a conventional RC PLL and the feed-forward path from the output of the phase frequency detector to the voltage controlled oscillator (VCO). The hybrid PLL essentially enhances the performance of the conventional feed-forward PLL by providing the RC filter whose components can be weighted to provide a dynamic response that is significantly less sensitive to parameter variation and which allows loop bandwidth optimization without sacrificing damping.
摘要翻译：提供了一种用于获得稳定的动态响应和阻尼因子和环路带宽的独立调整的混合锁相环（PLL）电路的设计结构。说明性实施例的混合PLL电路包括常规RC PLL的电阻/电容（RC）滤波器元件以及从相位频率检测器的输出到压控振荡器（VCO）的前馈路径。混合PLL本质上通过提供RC滤波器来增强常规前馈PLL的性能，RC滤波器的组件可以被加权，以提供对参数变化敏感性较低的动态响应，并且允许环路带宽优化而不牺牲阻尼。

44. 发明申请

US20080186104A1 INTERLEAVED VOLTAGE CONTROLLED OSCILLATOR 有权
公开(公告)号：US20080186104A1
公开(公告)日：2008-08-07
申请号：US12098490
申请日：2008-04-07
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
IPC分类号： H03K3/03
CPC分类号： H03L7/0995 , H03K3/0315 , H03K5/133
摘要： An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.

45. 发明申请

US20080136480A1 Extracting a Maximum Pulse Width of a Pulse Width Limiter 审中-公开
标题翻译：提取脉冲宽度限制器的最大脉冲宽度
公开(公告)号：US20080136480A1
公开(公告)日：2008-06-12
申请号：US12034039
申请日：2008-02-20
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K3/017 , H03K7/08
CPC分类号： H03K5/1534 , H03K5/156 , H03K2005/00293
摘要： An apparatus for extracting a maximum pulse width of a pulse width limiter is provided. The apparatus performs such extraction using a circuit that is configured to eliminate a majority of delay cells. The elimination of delay cells is made possible by replacing an OR gate in the circuit configuration with an edge triggered re-settable latch. The replacement of the OR gate with the edge triggered re-settable latch reduces the amount of chip area used in addition to the power consumption of the circuit.
摘要翻译：提供一种用于提取脉冲宽度限制器的最大脉冲宽度的装置。该装置使用被配置为消除大多数延迟单元的电路来执行这种提取。通过用边沿触发的可重新设置的锁存器替换电路配置中的或门，可以实现消除延迟单元。利用边沿触发的可重新设置的锁存器替换或门可以减少除了电路功耗之外使用的芯片面积。

46. 发明申请

US20070300082A1 Method for controlling operation of microprocessor which performs duty cycle correction process 失效
标题翻译：用于控制执行占空比校正处理的微处理器的操作的方法
公开(公告)号：US20070300082A1
公开(公告)日：2007-12-27
申请号：US11471819
申请日：2006-06-21
申请人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry , Sang Hoo Dhong
发明人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry , Sang Hoo Dhong
IPC分类号： G06F1/00
CPC分类号： G06F1/04
摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
摘要翻译：用于向微处理器提供电源电压的技术。在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。

47. 发明申请

US20070260409A1 Duty Cycle Measurement Apparatus and Method 审中-公开
标题翻译：占空比测量装置及方法
公开(公告)号：US20070260409A1
公开(公告)日：2007-11-08
申请号：US11777370
申请日：2007-07-13
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F19/00
CPC分类号： G01R29/02 , G01R31/2884
摘要： A mechanism for measuring duty cycle of a signal under test in an integrated circuit device, such as a microprocessor or system-on-a-chip is provided. The mechanism generates a frequency which is proportional to the duty cycle and which can be measured using common lab or manufacturing equipment. The mechanism may be implemented using simple circuits in a standard complementary metal oxide semiconductor process which requires very little area and can be powered off when it is not being used. The mechanism may include, for example, a low pass filter, a voltage divider for providing calibration reference voltage signals, a voltage to frequency converter, a frequency divider for dividing a frequency signal output so that the frequency of the signal is within a predetermined range, and an output driver and output pad. From the frequency output signal, a duty cycle of the signal under test may be calculated using off-chip equipment.
摘要翻译：提供了一种用于测量诸如微处理器或片上系统的集成电路器件中被测信号占空比的机构。该机制产生与占空比成比例的频率，可以使用普通实验室或制造设备测量。该机构可以使用标准互补金属氧化物半导体工艺中的简单电路来实现，其需要非常小的面积并且可以在不使用时关闭电源。该机构可以包括例如低通滤波器，用于提供校准参考电压信号的分压器，电压到频率转换器，用于分频频率信号输出的分频器，使得信号的频率在预定范围内，以及输出驱动器和输出板。从频率输出信号，可以使用片外设备来计算被测信号的占空比。

48. 发明申请

US20070255517A1 METHOD AND APPARATUS FOR ON-CHIP DUTY CYCLE MEASUREMENT 失效
标题翻译：用于芯片周期测量的方法和装置
公开(公告)号：US20070255517A1
公开(公告)日：2007-11-01
申请号：US11380982
申请日：2006-05-01
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F19/00
CPC分类号： G01R31/31727 , G01R31/3004 , G01R31/31726
摘要： The disclosed methodology and apparatus measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit located “on-chip”, namely on an integrated circuit (IC) in which the DCM circuit is incorporated. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.
摘要翻译：所公开的方法和装置测量时钟电路提供给位于“片上”的占空比测量（DCM）电路的参考时钟信号的占空比，即集成电路（IC），其中并入DCM电路。在一个实施例中，DCM电路包括由电荷泵驱动的电容器。参考时钟信号驱动电荷泵。时钟电路在多个已知的占空比值之间改变参考时钟信号的占空比。 DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号占空比的新电压值。控制软件访问数据存储，以确定测试时钟信号对应的占空比。

49. 发明授权

US07260491B2 Duty cycle measurement apparatus and method 失效
公开(公告)号：US07260491B2
公开(公告)日：2007-08-21
申请号：US11260570
申请日：2005-10-27
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F19/00
CPC分类号： G01R29/02 , G01R31/2884
摘要： A mechanism for measuring duty cycle of a signal under test in an integrated circuit device, such as a microprocessor or system-on-a-chip is provided. The mechanism generates a frequency which is proportional to the duty cycle and which can be measured using common lab or manufacturing equipment. The mechanism may be implemented using simple circuits in a standard complementary metal oxide semiconductor process which requires very little area and can be powered off when it is not being used. The mechanism may include, for example, a low pass filter, a voltage divider for providing calibration reference voltage signals, a voltage to frequency converter, a frequency divider for dividing a frequency signal output so that the frequency of the signal is within a predetermined range, and an output driver and output pad. From the frequency output signal, a duty cycle of the signal under test may be calculated using off-chip equipment.

50. 发明授权

US07245172B2 Level shifter apparatus and method for minimizing duty cycle distortion 失效
标题翻译：用于最小化占空比失真的电平移位器装置和方法
公开(公告)号：US07245172B2
公开(公告)日：2007-07-17
申请号：US11269245
申请日：2005-11-08
申请人： David W. Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A level shifter apparatus and method for minimizing duty cycle distortion are provided. The level shifter includes a bank of comparators each having an associated threshold built into it. The comparators compare a difference in source voltages for two power domains to these built-in thresholds and output a signal indicative of whether the threshold is exceeded. The output signals from the comparators are provided to a thermometric decoder which generates control signals based on these output signals. The control signals are used to control stages in a level shifter for modifying the voltage output of the level shifter. Individual stages may be enabled to thereby monotonically modify the voltage output of the level shifter and thereby decrease a time required to achieve a voltage having a level that causes a state change in a driven circuit. As a result, duty cycle distortion is minimized and maximum operational frequency is increased.
摘要翻译：提供了一种用于最小化占空比失真的电平移位器装置和方法。电平移位器包括一组比较器，每个比较器具有内置在其中的相关联的阈值。比较器将两个功率域的源电压差与这些内置阈值进行比较，并输出一个指示阈值是否超过的信号。来自比较器的输出信号被提供给基于这些输出信号产生控制信号的温度测量解码器。控制信号用于控制电平移位器中用于修改电平移位器的电压输出的级。单个级可以被使能，从而单调地修改电平转换器的电压输出，从而减少实现具有使驱动电路中的状态变化的电平的电压所需的时间。结果，占空比失真被最小化并且最大的操作频率增加。

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