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41. 发明授权

US07564091B2 Memory device and methods for its fabrication 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US07564091B2
公开(公告)日：2009-07-21
申请号：US12199692
申请日：2008-08-27
申请人： Chungho Lee , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Meng Ding
发明人： Chungho Lee , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Meng Ding
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： H01L21/28282 , H01L29/42332 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.
摘要翻译：提供半导体存储器件及其制造方法。根据本发明的一个实施例，该方法包括以下步骤：形成栅极绝缘体和覆盖半导体衬底的栅电极。蚀刻栅极绝缘体以在栅电极的边缘下方形成底切开口，并且底切开口填充有包括夹在氧化物层和氮化物层之间的电荷捕获层的分层结构。掺杂半导体衬底的区域以形成与栅电极对准的位线，并且沉积并图案化导电层以形成耦合到栅电极的字线。

42. 发明授权

US07439141B2 Shallow trench isolation approach for improved STI corner rounding 有权
标题翻译：浅沟隔离方法可改善STI拐角四舍五入
公开(公告)号：US07439141B2
公开(公告)日：2008-10-21
申请号：US10277395
申请日：2002-10-22
申请人： Unsoon Kim , Yu Sun , Hiroyuki Kinoshita , Kuo-Tung Chang , Harpreet K. Sachar , Mark S. Chang
发明人： Unsoon Kim , Yu Sun , Hiroyuki Kinoshita , Kuo-Tung Chang , Harpreet K. Sachar , Mark S. Chang
IPC分类号： H01L21/00
CPC分类号： H01L21/76235
摘要： A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. The method further includes performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are substantially rounded by the four oxidation processes.
摘要翻译：公开了一种用于在半导体制造期间进行浅沟槽隔离的方法，其改善沟槽角圆化。该方法包括将沟槽蚀刻到有源区域之间的硅衬底中，并在沟槽上执行双衬层氧化工艺。该方法还包括对活性区域进行双重牺牲氧化处理，其中沟槽的角通过四个氧化过程基本上被圆化。

43. 发明申请

US20080153222A1 METHODS FOR FABRICATING A SPLIT CHARGE STORAGE NODE SEMICONDUCTOR MEMORY 有权
标题翻译：用于制造分离充电储存节点半导体存储器的方法
公开(公告)号：US20080153222A1
公开(公告)日：2008-06-26
申请号：US11614048
申请日：2006-12-20
申请人： Chungho Lee , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Sugimo Rinji , Wei Zheng
发明人： Chungho Lee , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Sugimo Rinji , Wei Zheng
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L29/792
摘要： Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.
摘要翻译：提供了用于制造分离电荷存储节点半导体存储器件的方法。根据一个实施例，该方法包括以下步骤：在半导体衬底上形成具有第一物理厚度和第一有效氧化物厚度的栅极绝缘体层，并形成具有覆盖栅极绝缘体层的第一边缘和第二边缘的控制栅极电极。栅极绝缘体层被蚀刻以在控制栅电极的边缘处形成第一和第二底切区域，第一和第二底切区域各自暴露半导体衬底的一部分和控制栅电极的下侧部分。第一和第二电荷存储节点形成在底切区域中，每个电荷存储节点包括具有基本上等于第一物理厚度的物理厚度和小于第一有效氧化物的有效氧化物厚度的氧化物存储材料 - 氧化物结构厚度。

44. 发明申请

US20080149999A1 SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION 有权
标题翻译：包含双电池存储器的半导体存储器及其制造方法
公开(公告)号：US20080149999A1
公开(公告)日：2008-06-26
申请号：US11613513
申请日：2006-12-20
申请人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
发明人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/42332 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.
摘要翻译：提供了双电荷存储节点存储器件及其制造方法。在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。在第二部分上形成一层半导体材料。第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层和第二电介质层。将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

45. 发明申请

US20070026675A1 System and method for improving mesa width in a semiconductor device 有权
标题翻译：用于改善半导体器件中的台面宽度的系统和方法
公开(公告)号：US20070026675A1
公开(公告)日：2007-02-01
申请号：US11193409
申请日：2005-08-01
申请人： Unsoon Kim , Angela Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
发明人： Unsoon Kim , Angela Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
IPC分类号： H01L21/302
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11521 , H01L27/11531
摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成氮化物层。蚀刻氮化物层和衬底以形成沟槽。在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。沟槽填充有氧化物材料。从存储器件剥离氮化物层，在沟槽上方形成台面。

46. 发明授权

US07029975B1 Method and apparatus for eliminating word line bending by source side implantation 有权
标题翻译：通过源侧植入消除字线弯曲的方法和装置
公开(公告)号：US07029975B1
公开(公告)日：2006-04-18
申请号：US10839561
申请日：2004-05-04
申请人： Shenqing Fang , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani
发明人： Shenqing Fang , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/513
摘要： A method and apparatus for coupling to a source line is disclosed. A semiconductor structure having an array of memory cells arranged in rows and columns is described. The array of memory cells includes a source region that is implanted with n-type dopants isolated between an adjoining pair of the non-intersecting STI regions and isolated from a drain region during the implantation. A source contact is located along a row of drain contacts that are coupled to drain regions of a row of memory cells and the source contact is coupled to the source region for providing electrical coupling with a plurality of source lines. The isolating of the implanted source region from the drain region during the implanting enables coupling of the source contact to the source lines while maintaining the n-type dopants between the STI regions and avoiding lateral diffusion to a bit-line.
摘要翻译：公开了一种用于耦合到源极线的方法和装置。描述了具有排列成行和列的存储单元阵列的半导体结构。存储单元阵列包括源区域，其注入在相邻的一对不相交的STI区域之间隔离并在植入期间与漏区隔离的n型掺杂剂。源极触点沿着一排漏极触点排列，其被连接到一行存储器单元的漏极区域，并且源极触点耦合到源极区域以提供与多个源极线的电耦合。在植入期间将注入的源极区域与漏极区域隔离使得能够将源极接触耦合到源极线，同时保持STI区域之间的n型掺杂剂并且避免横向扩散到位线。

47. 发明申请

US20060035431A1 Memory cell with reduced DIBL and Vss resistance 有权
标题翻译：具有降低的DIBL和Vss电阻的存储单元
公开(公告)号：US20060035431A1
公开(公告)日：2006-02-16
申请号：US10915771
申请日：2004-08-11
申请人： Shenqing Fang , Kuo-Tung Chang , Pavel Fastenko , Zhigang Wang
发明人： Shenqing Fang , Kuo-Tung Chang , Pavel Fastenko , Zhigang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/66825
摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory cell on substrate comprises a step of forming a spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in substrate. The method further comprises forming a high energy implant doped region adjacent to the spacer in the source region of substrate. The method further comprises forming a recess in a source region of the substrate, where the recess has a sidewall, a bottom, and a depth, and where the sidewall of the recess is situated adjacent to a source of the floating gate memory cell. According to this exemplary embodiment, the spacer causes the source to have a reduced lateral straggle and diffusion in the channel region, which causes a reduction in drain induced barrier lowering (DIBL) in the floating gate memory cell.
摘要翻译：根据一个示例性实施例，用于在衬底上制造浮动栅极存储器单元的方法包括形成与层叠栅极结构的源极侧壁相邻的间隔物的步骤，其中堆叠的栅极结构位于衬底中的沟道区域之上。该方法还包括在衬底的源区中形成与间隔物相邻的高能注入掺杂区。该方法还包括在衬底的源极区域中形成凹部，其中凹部具有侧壁，底部和深度，并且凹部的侧壁位于与浮动栅极存储单元的源极相邻的位置。根据该示例性实施例，间隔件导致源极在通道区域中具有减小的横向偏移和扩散，这导致浮动栅极存储单元中的漏极感应势垒降低（DIBL）的减小。

48. 发明授权

US06803272B1 Use of high-K dielectric material in modified ONO structure for semiconductor devices 有权
标题翻译：在改性ONO结构中使用高K介电材料用于半导体器件
公开(公告)号：US06803272B1
公开(公告)日：2004-10-12
申请号：US10646080
申请日：2003-08-22
申请人： Arvind Halliyal , Mark T. Ramsbey , Kuo-Tung Chang , Nicholas H. Tripsas , Robert B. Ogle
发明人： Arvind Halliyal , Mark T. Ramsbey , Kuo-Tung Chang , Nicholas H. Tripsas , Robert B. Ogle
IPC分类号： H01L218242
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66833 , H01L29/7923
摘要： A process for fabrication of a semiconductor device including a modified ONO structure, comprising forming the modified ONO structure by providing a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; depositing a layer comprising a high-K dielectric material on the first oxide layer; and forming a top oxide layer on the layer comprising a high-K dielectric material. The semiconductor device may be, e.g., a MIRRORBIT™ two-bit EEPROM device or a floating gate flash device including a modified ONO structure.
摘要翻译：一种制造包括修饰的ONO结构的半导体器件的方法，包括通过提供半导体衬底形成修饰的ONO结构; 在所述半导体衬底上形成第一氧化物层; 在所述第一氧化物层上沉积包含高K电介质材料的层; 以及在包含高K电介质材料的层上形成顶部氧化物层。半导体器件可以是例如MIRRORBIT TM 2位EEPROM器件或包括修改的ONO结构的浮动栅极闪存器件。

49. 发明授权

US06576487B1 Method to distinguish an STI outer edge current component with an STI normal current component 失效
标题翻译：区分STI外缘电流分量与STI正常电流分量的方法
公开(公告)号：US06576487B1
公开(公告)日：2003-06-10
申请号：US10126363
申请日：2002-04-19
申请人： Zhigang Wang , Harpreet Kaur Sachar , Kuo-Tung Chang
发明人： Zhigang Wang , Harpreet Kaur Sachar , Kuo-Tung Chang
IPC分类号： G01R3126
CPC分类号： H01L22/34 , H01L21/76229 , H01L21/76232
摘要： The present invention details a method which characterizes an STI fabrication process, and more particularly provides information relating to a variation in the STI sidewall profile between trenches in a middle portion of an array and a trench on an outer portion thereof. The method comprises forming two STI arrays with an STI fabrication process, forming a conductive layer over each array, biasing each conductive layer and determining a current associated therewith. The two current are then utilized to ascertain the variation of interest.
摘要翻译：本发明详细描述了一种表征STI制造工艺的方法，并且更具体地提供了与阵列的中间部分中的沟槽和其外部部分上的沟槽之间的STI侧壁轮廓变化有关的信息。该方法包括用STI制造工艺形成两个STI阵列，在每个阵列上形成导电层，偏置每个导电层并确定与之相关联的电流。然后利用两个电流来确定兴趣的变化。

50. 发明授权

US5981340A Method of building an EPROM cell without drain disturb and reduced select gate resistance 失效
标题翻译：构建EPROM单元而无漏极干扰和降低选择栅极电阻的方法
公开(公告)号：US5981340A
公开(公告)日：1999-11-09
申请号：US939397
申请日：1997-09-29
申请人： Kuo-Tung Chang , Erwin J. Prinz , Craig T. Swift
发明人： Kuo-Tung Chang , Erwin J. Prinz , Craig T. Swift
IPC分类号： G11C16/04 , H01L27/115 , H01L21/336
CPC分类号： H01L27/115 , G11C16/0433
摘要： A semiconductor device (70) includes a memory cell having a select transistor (67) and a storage transistor (65) having a relatively uniform tunnel dielectric thickness under both the floating gate (651) of the storage transistor and the select gate (671) of the select transistor (67). The select transistor (67) is adjacent to the drain region (68) for the memory cell to nearly eliminate a drain disturb problem. During programming, the control gate (652) is at a negative potential, and the drain region (68) is at a positive potential. The drain potential is sufficiently low to not degrade the tunnel dielectric layer (42) of the select transistor (67). During erase, a positive potential is applied to the control gate (652). The relatively uniform tunnel dielectric layer (42) thickness of the select transistor (67) allows for a faster operating device by increasing the read current of the memory device.
摘要翻译：半导体器件（70）包括具有在存储晶体管的浮动栅极（651）和选择栅极（671）两者下具有相对均匀的隧道电介质厚度的选择晶体管（67）和存储晶体管（65）的存储单元，的选择晶体管（67）。选择晶体管（67）与用于存储单元的漏极区域（68）相邻，几乎消除了漏极干扰问题。在编程期间，控制栅极（652）处于负电位，漏区（68）处于正电位。漏极电位足够低以不降低选择晶体管（67）的隧道介电层（42）。在擦除期间，向控制栅极施加正电位（652）。选择晶体管（67）的相对均匀的隧道介电层（42）的厚度通过增加存储器件的读取电流而允许更快的操作器件。

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