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41. 发明授权

US07291531B2 Method of fabricating semiconductor device having capacitor 有权
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US07291531B2
公开(公告)日：2007-11-06
申请号：US11048995
申请日：2005-02-02
申请人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中，接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层电极在下电极上。

42. 发明授权

US07256143B2 Semiconductor device having self-aligned contact plug and method for fabricating the same 有权
标题翻译：具有自对准接触插塞的半导体器件及其制造方法
公开(公告)号：US07256143B2
公开(公告)日：2007-08-14
申请号：US11058670
申请日：2005-02-15
申请人： Myeong-Cheol Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Young Son
发明人： Myeong-Cheol Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Young Son
IPC分类号： H01L21/31
CPC分类号： H01L21/76831 , H01L21/76897 , H01L23/5226 , H01L27/10814 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a capping layer are sequentially deposited on an insulating layer over a semiconductor substrate. The first interlayer insulating layer fills spaces between the conductive patterns and has a height such that when the first interlayer insulating layer is placed on the insulating layer, the first interlayer insulating layer is lower than a top surface of the capping layer but higher than a top surface of the conductive layer. The first spacer surrounds the outer surface of the capping layer on the first interlayer insulating layer. The second interlayer insulating layer covers the first interlayer insulating layer, the capping layer, and the first spacer and has a planarized top surface. The contact plug passes through the second interlayer insulating layer, the first interlayer insulating layer, and the insulating layer between the conductive patterns, is electrically connected to the semiconductor substrate, has an outerwall surrounded by a second spacer, and is self-aligned with the capping layer.
摘要翻译：提供一种具有自对准接触插塞的半导体器件和制造半导体器件的方法。半导体器件包括导电图案，第一层间绝缘层，第一间隔物，第二层间绝缘层和接触塞。在每个导电图案中，导电层和覆盖层依次沉积在半导体衬底上的绝缘层上。第一层间绝缘层填充导电图案之间的空间，并且具有这样的高度，使得当第一层间绝缘层放置在绝缘层上时，第一层间绝缘层低于封盖层的顶表面，但高于顶部导电层的表面。第一间隔件包围第一层间绝缘层上的覆盖层的外表面。第二层间绝缘层覆盖第一层间绝缘层，覆盖层和第一间隔物，并且具有平坦化的顶表面。接触插塞穿过第二层间绝缘层，第一层间绝缘层和导电图案之间的绝缘层电连接到半导体衬底，具有由第二间隔物包围的外壁，并且与盖层

43. 发明申请

US20060293781A1 Method of optimizing seasoning recipe for etch process 审中-公开
公开(公告)号：US20060293781A1
公开(公告)日：2006-12-28
申请号：US11510987
申请日：2006-08-28
申请人： Hong Cho , Chang-Jin Kang , Kyeong-Koo Chi , Cheol-Kyu Lee , Hye-Jin Jo
发明人： Hong Cho , Chang-Jin Kang , Kyeong-Koo Chi , Cheol-Kyu Lee , Hye-Jin Jo
IPC分类号： G06F19/00
CPC分类号： H01L21/67253 , H01L21/32137 , H01L21/67069 , H01L22/20
摘要： A method for optimizing a seasoning recipe for a dry etch process. The method includes setting a critical value of reproducibility, a main etch recipe, and a preliminary seasoning recipe. A test wafer is then etched using the preliminary seasoning recipe in a dry etch chamber. Next, a main etch process is performed with respect to at least 10 run wafers in the dry etch chamber using the main etch recipe and an end-point detection time for each wafer is determined. An initial dispersion and a standard deviation are then determined using the determined end-point detection times. The critical value of reproducibility is then compared to the initial dispersion. If the initial dispersion is equal to or less than the critical value of reproducibility, the preliminary seasoning recipe is used as the seasoning recipe, otherwise the preliminary seasoning recipe is modified and the process is repeated until an optimal seasoning recipe is determined.

44. 发明授权

US07125766B2 Method of forming capacitor for semiconductor device 有权
标题翻译：形成半导体器件电容器的方法
公开(公告)号：US07125766B2
公开(公告)日：2006-10-24
申请号：US11062546
申请日：2005-02-23
申请人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Chi
发明人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Chi
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10814 , H01L27/10817 , H01L27/10855
摘要： A method of forming a capacitor for a semiconductor device is disclosed. According to the method, a silicon germanium layer and an oxide layer are used as mold layers for forming a storage electrode. The oxide layer and the silicon germanium layer are anisotropically etched to form an opening and then the silicon germanium layer is further isotropically etched to form a recessed portion of the opening, such that the recessed portion of the opening formed in the silicon germanium layer is wider than at least some portion of the opening through the oxide layer. Thus, the mold layers are used to form a storage electrode having a lower portion which is wider than an upper portion thereof.
摘要翻译：公开了一种形成用于半导体器件的电容器的方法。根据该方法，使用硅锗层和氧化物层作为用于形成存储电极的模具层。各向异性蚀刻氧化物层和硅锗层以形成开口，然后进一步各向同性地蚀刻硅锗层以形成开口的凹部，使得形成在硅锗层中的开口的凹部变宽比通过氧化物层的开口的至少一部分。因此，模具层用于形成具有比其上部宽的下部的存储电极。

45. 发明授权

US07118926B2 Method of optimizing seasoning recipe for etch process 失效
标题翻译：优化蚀刻工艺调味配方的方法
公开(公告)号：US07118926B2
公开(公告)日：2006-10-10
申请号：US10652403
申请日：2003-08-29
申请人： Hong Cho , Chang-Jin Kang , Kyeong-Koo Chi , Cheol-Kyu Lee , Hye-Jin Jo
发明人： Hong Cho , Chang-Jin Kang , Kyeong-Koo Chi , Cheol-Kyu Lee , Hye-Jin Jo
IPC分类号： H01L21/00
CPC分类号： H01L21/67253 , H01L21/32137 , H01L21/67069 , H01L22/20
摘要： A method for optimizing a seasoning recipe for a dry etch process. The method includes setting a critical value of reproducibility, a main etch recipe, and a preliminary seasoning recipe. A test wafer is then etched using the preliminary seasoning recipe in a dry etch chamber. Next, a main etch process is performed with respect to at least 10 run wafers in the dry etch chamber using the main etch recipe and an end-point detection time for each wafer is determined. An initial dispersion and a standard deviation are then determined using the determined end-point detection times. The critical value of reproducibility is then compared to the initial dispersion. If the initial dispersion is equal to or less than the critical value of reproducibility, the preliminary seasoning recipe is used as the seasoning recipe, otherwise the preliminary seasoning recipe is modified and the process is repeated until an optimal seasoning recipe is determined.
摘要翻译：一种优化干蚀刻工艺调味配方的方法。该方法包括设置重现性的临界值，主蚀刻配方和初步调味配方。然后使用干蚀刻室中的初步调味配方蚀刻测试晶片。接下来，使用主蚀刻配方对干蚀刻室中的至少10个运行晶片执行主蚀刻处理，并且确定每个晶片的终点检测时间。然后使用确定的终点检测时间确定初始色散和标准偏差。然后将重现性的临界值与初始色散进行比较。如果初始分散度等于或小于再现性的临界值，则使用初步调味配方作为调味配方，否则初步调味配方被修改，重复该过程直到确定最佳调味配方。

46. 发明申请

US20060079076A1 Methods of forming field effect transistors having t-shaped gate electrodes using carbon-based etching masks 有权
公开(公告)号：US20060079076A1
公开(公告)日：2006-04-13
申请号：US11247937
申请日：2005-10-11
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/1037 , H01L21/823437 , H01L21/823456 , H01L29/76
摘要： Methods of forming field effect transistors include forming a first electrically insulating layer comprising mostly carbon on a surface of a semiconductor substrate and patterning the first electrically insulating layer to define an opening therein. A trench is formed in the substrate by etching the surface of the substrate using the patterned first electrically insulating layer as an etching mask. The trench is filled with a gate electrode. The first electrically insulating layer is patterned in an ambient containing oxygen. This oxygen-containing ambient supports further oxidation of trench-based isolation regions within the substrate when they are exposed by openings within the first electrically insulating layer.

47. 发明申请

US20060024932A1 Methods of forming semiconductor devices including removing a thickness of a polysilicon gate layer 审中-公开
标题翻译：形成半导体器件的方法包括去除多晶硅栅极层的厚度
公开(公告)号：US20060024932A1
公开(公告)日：2006-02-02
申请号：US11191488
申请日：2005-07-28
申请人： Heung-Sik Park , Kyeong-Koo Chi , Chang-Jin Kang
发明人： Heung-Sik Park , Kyeong-Koo Chi , Chang-Jin Kang
IPC分类号： H01L21/425
CPC分类号： H01L21/823842
摘要： Embodiments of the present invention provide methods of forming a semiconductor device including forming a polysilicon layer on a semiconductor substrate and doping the polysilicon layer with P-type impurities. The semiconductor substrate including the polysilicon layer is annealed and then an upper portion having a first thickness of the annealed polysilicon layer doped with the P-type impurities is removed. The first thickness is selected to remove defects formed in the polysilicon layer during doping and/or annealing thereof.
摘要翻译：本发明的实施例提供了形成半导体器件的方法，该半导体器件包括在半导体衬底上形成多晶硅层，并用P型杂质掺杂多晶硅层。包括多晶硅层的半导体衬底被退火，然后去除掺杂有P型杂质的退火多晶硅层的第一厚度的上部。选择第一厚度以去除在其掺杂和/或退火期间在多晶硅层中形成的缺陷。

48. 发明申请

US20050282363A1 Method of forming fine pattern of semiconductor device using SiGe layer as sacrificial layer, and method of forming self-aligned contacts using the same 有权
标题翻译：使用SiGe层作为牺牲层形成精细图案的半导体器件的方法以及使用其形成自对准触点的方法
公开(公告)号：US20050282363A1
公开(公告)日：2005-12-22
申请号：US11157435
申请日：2005-06-21
申请人： Keun-Hee Bai , Kyeong-Koo Chi , Chang-Jin Kang , Cheol-Kyu Lee
发明人： Keun-Hee Bai , Kyeong-Koo Chi , Chang-Jin Kang , Cheol-Kyu Lee
IPC分类号： H01L21/027 , H01L21/033 , H01L21/36 , H01L21/469 , H01L21/60
CPC分类号： H01L21/0331 , H01L21/0332 , H01L21/76897
摘要： There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.
摘要翻译：提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，并且形成硅锗（Si 1-Si） xTi）x牺牲层，其具有等于或高于至少导电线结构的高度的高度，在基底的整个表面上。然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。

49. 发明申请

US20050245026A1 Method of forming capacitor for semiconductor device 有权
标题翻译：形成半导体器件电容器的方法
公开(公告)号：US20050245026A1
公开(公告)日：2005-11-03
申请号：US11062546
申请日：2005-02-23
申请人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Chi
发明人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Chi
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242
CPC分类号： H01L28/91 , H01L27/10814 , H01L27/10817 , H01L27/10855
摘要： A method of forming a capacitor for a semiconductor device is disclosed. According to the method, a silicon germanium layer and an oxide layer are used as mold layers for forming a storage electrode. The oxide layer and the silicon germanium layer are anisotropically etched to form an opening and then the silicon germanium layer is further isotropically etched to form a recessed portion of the opening, such that the recessed portion of the opening formed in the silicon germanium layer is wider than at least some portion of the opening through the oxide layer. Thus, the mold layers are used to form a storage electrode having a lower portion which is wider than an upper portion thereof.
摘要翻译：公开了一种形成用于半导体器件的电容器的方法。根据该方法，使用硅锗层和氧化物层作为用于形成存储电极的模具层。各向异性蚀刻氧化物层和硅锗层以形成开口，然后进一步各向同性地蚀刻硅锗层以形成开口的凹部，使得形成在硅锗层中的开口的凹部变宽比通过氧化物层的开口的至少一部分。因此，模具层用于形成具有比其上部宽的下部的存储电极。

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