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41. 发明授权

US07238579B2 Semiconductor device for reducing photovolatic current 失效
标题翻译：用于降低光伏电流的半导体器件
公开(公告)号：US07238579B2
公开(公告)日：2007-07-03
申请号：US11003279
申请日：2004-12-03
申请人： Bradley P. Smith , Edward O. Travis
发明人： Bradley P. Smith , Edward O. Travis
IPC分类号： H01L21/8236
CPC分类号： H01L23/552 , H01L2924/0002 , Y02P80/30 , H01L2924/00
摘要： A semiconductor device that has a common border between P and N wells is susceptible to photovoltaic current that is believed to be primarily generated from photons that strike this common border. Photons that strike the border are believed to create electron/hole pairs that separate when created at the PN junction of the border. The photovoltaic current can have a sufficient current density to be destructive to the metal connections to a well if the area of these metal connections to the well is small relative to the length of the border. This photovoltaic current can be reduced below destructive levels by covering the common border sufficiently to reduce the number of photons hitting the common border. The surface area of the connections can also be increased to alleviate the problem.
摘要翻译：在P和N阱之间具有共同边界的半导体器件易于被认为主要由撞击该共同边界的光子产生的光电流。据认为，在边界PN结处产生的电子/空穴对被分离出来。如果与井的这些金属连接的面积相对于边界的长度小，则光电流可以具有足够的电流密度来破坏与阱的金属连接。通过充分覆盖公共边界以减少击中共同边界的光子的数量，该光电流可以降低到破坏性水平以下。连接的表面积也可以增加以减轻问题。

42. 发明授权

US09122829B2 Stress migration mitigation 有权
标题翻译：压力迁移缓解
公开(公告)号：US09122829B2
公开(公告)日：2015-09-01
申请号：US13956044
申请日：2013-07-31
申请人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
发明人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F2217/76 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A computer-implemented method of configuring a semiconductor device includes identifying an interconnect having an interconnect path length greater than a stress-induced void formation characteristic length of the semiconductor device, and placing, with a processor, a conductive structure adjacent the interconnect to define a pair of segments of the interconnect. Each segment has a length no greater than the stress-induced void formation characteristic length of the interconnect, and the conductive structure is selected from the group consisting of a decoy via connected to the interconnect, a floating tile disposed along the interconnect, a tab that laterally extends outward from the interconnect, and a jumper from a first metal layer in which the interconnect is disposed to a second metal layer.
摘要翻译：配置半导体器件的计算机实现的方法包括识别具有大于半导体器件的应力引起的空隙形成特征长度的互连路径长度的互连，以及与处理器相邻配置的导电结构，以定义互连的一对段。每个段的长度不大于互连的应力诱导的空隙形成特征长度，并且导电结构选自连接到互连的诱饵通道，沿互连设置的浮动瓦，横向地从互连件向外延伸，并且从其中布置有互连的第一金属层的跳线到第二金属层。

43. 发明申请

US20150091178A1 3D DEVICE PACKAGING USING THROUGH-SUBSTRATE PILLARS 有权
标题翻译： 3D设备包装使用通过衬底支柱
公开(公告)号：US20150091178A1
公开(公告)日：2015-04-02
申请号：US14039622
申请日：2013-09-27
申请人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
发明人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
IPC分类号： H01L23/00 , H01L25/00 , H01L23/48
CPC分类号： H01L25/50 , H01L21/304 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05557 , H01L2224/05568 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2224/05686 , H01L2224/0569 , H01L2224/13023 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/14131 , H01L2224/14133 , H01L2224/14135 , H01L2224/1414 , H01L2224/14517 , H01L2224/16111 , H01L2224/16147 , H01L2224/48463 , H01L2224/73257 , H01L2224/8114 , H01L2224/81815 , H01L2224/92 , H01L2224/9202 , H01L2224/92227 , H01L2224/94 , H01L2225/06513 , H01L2225/06568 , H01L2225/06596 , H01L2924/00014 , H01L2924/12042 , H01L2924/14 , H01L2924/1461 , H01L2924/15788 , H01L2924/384 , H01L2924/00 , H01L2224/03 , H01L21/78 , H01L21/56 , H01L2224/81 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for 3D device packaging utilizes through-substrate pillars to mechanically and electrically bond two or more dice. The first die includes a set of access holes extending from a surface of the first die to a set of pads at a metal layer of the first die. The second die includes a set of metal pillars. The first die and the second die are stacked such that each metal pillar extends from a surface of the second die to a corresponding pad via a corresponding access hole. The first die and second die are mechanically and electrically bonded via solder joints formed between the metal pillars and the corresponding pads.
摘要翻译：用于3D设备封装的方法利用贯穿基板支柱将两个或更多个骰子机械地和电气地接合。第一管芯包括从第一管芯的表面延伸到第一管芯的金属层处的一组焊盘的一组入口孔。第二个模具包括一套金属支柱。第一管芯和第二管芯被堆叠成使得每个金属柱经由相应的通孔从第二管芯的表面延伸到相应的焊盘。第一模具和第二模具通过形成在金属柱和相应焊盘之间的焊接点机械地和电连接。

44. 发明授权

US08856705B2 Mismatch verification device and methods thereof 有权
标题翻译：不匹配验证装置及其方法
公开(公告)号：US08856705B2
公开(公告)日：2014-10-07
申请号：US13466642
申请日：2012-05-08
申请人： Mehul D. Shroff , Sanjay R. Parihar , Edward O. Travis
发明人： Mehul D. Shroff , Sanjay R. Parihar , Edward O. Travis
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method can include identifying a device design comprising first and second instantiations of a device, identifying a layer of the device design, identifying a first region of the device design for the first instantiation based on the layer of the first instantiation, and a second region of the device design for the second instantiation based on the layer of the second instantiation. identifying a first compare layer of the device design that comprises a plurality of first compare features including a first compared feature within the first region and a second compared feature within the second region, determining a difference between the first compared feature and the second compared feature, and determining if the difference meets a tolerance to determine if the first instantiation matches the second instantiation.
摘要翻译：方法可以包括识别包括设备的第一和第二实例化的设备设计，识别设备设计的层，基于第一实例的层识别第一实例化的设备设计的第一区域，以及第二区域基于第二实例化层的第二实例化设备设计。识别所述设备设计的第一比较层，其包括多个第一比较特征，所述第一比较特征包括所述第一区域内的第一比较特征和所述第二区域内的第二比较特征，确定所述第一比较特征与所述第二比较特征之间的差，以及确定所述差是否满足公差以确定所述第一实例是否与所述第二实例化匹配。

45. 发明授权

US08796841B2 Semiconductor device with embedded heat spreading 有权
标题翻译：具有嵌入式散热的半导体器件
公开(公告)号：US08796841B2
公开(公告)日：2014-08-05
申请号：US13442014
申请日：2012-04-09
申请人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
发明人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
IPC分类号： H01L23/10
CPC分类号： H01L23/373 , H01L21/768 , H01L23/3677 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate and a plurality of clock drivers, wherein the plurality of clock drivers comprises substantially all clock drivers of the semiconductor device, and an interconnect region over the semiconductor substrate, wherein the interconnect region comprises a plurality of heat spreaders, wherein at least 25% of the plurality of clock drivers have a corresponding heat spreader of the plurality of heat spreaders. Each corresponding heat spreader of the plurality of heat spreaders covers at least 50% of a transistor within a corresponding clock driver of the plurality of clock drivers and extends across at least 70% of a perimeter of the transistor within the corresponding clock driver.
摘要翻译：半导体器件包括半导体衬底和多个时钟驱动器，其中多个时钟驱动器包括半导体器件的基本上所有的时钟驱动器，以及半导体衬底上的互连区域，其中互连区域包括多个散热器，其中所述多个时钟驱动器中的至少25％具有所述多个散热器中相应的散热器。多个散热器的每个相应的散热器覆盖多个时钟驱动器的对应的时钟驱动器内的至少50％的晶体管，并延伸到对应的时钟驱动器内的晶体管的周边的至少70％。

46. 发明授权

US08736071B2 Semiconductor device with vias on a bridge connecting two buses 有权
标题翻译：半桥设备，通孔连接两条总线桥
公开(公告)号：US08736071B2
公开(公告)日：2014-05-27
申请号：US13285073
申请日：2011-10-31
申请人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
发明人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
IPC分类号： H01L23/48
CPC分类号： G06F13/4027 , G06F17/5077 , H01L23/5221 , H01L23/528 , H01L23/5283 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses. At least N plus one (N+1) vias are coupled between every one of the conductive bridges and a respective feature in an integrated circuit when: (1) a width of the respective conductive bridge is less than a width of each of the at least two portions of the at least one of the conductive buses to which the respective conductive bridge is coupled, and (2) a distance along the respective conductive bridge and at least one of the vias is less than a critical distance. N is a number of conductive couplings between the respective one of the conductive bridges and the at least one of the conductive buses.
摘要翻译：半导体器件包括导电总线和导电桥。相应的导电桥与至少一个导电总线的至少两个部分导电耦合。当以下情况下，至少N + 1个（N + 1）通孔耦合在每个导电桥和集成电路中的相应特征之间：（1）相应导电桥的宽度小于每个导体桥的宽度所述至少一个导电总线的至少一个导体总线的至少两个部分相互连接，并且（2）沿相应导电桥和至少一个通孔的距离小于临界距离。 N是在相应的一个导电桥和至少一个导电总线之间的多个导电耦合。

47. 发明授权

US08640072B1 Method for forming an electrical connection between metal layers 有权
标题翻译：在金属层之间形成电连接的方法
公开(公告)号：US08640072B1
公开(公告)日：2014-01-28
申请号：US13562538
申请日：2012-07-31
申请人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
发明人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
IPC分类号： G06F17/50 , H01L21/4763 , H01L29/40
CPC分类号： H01L21/76877 , G06F17/5077 , H01L21/4763 , H01L21/76816 , H01L23/5226 , H01L29/401 , H01L2924/0002 , H01L2924/00
摘要： A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero.
摘要翻译：一种方法包括在第一金属层和第二金属层之间形成连接。第二金属层在第一金属层之上。识别用于第一金属层和第二金属层之间的第一通孔的通孔位置。确定第一个额外通孔的附加位置。第一个额外的通孔被确定为压力迁移问题所必需的。确定第二个额外通孔所需的附加位置。第二个额外的通孔被确定为电迁移问题所必需的。第一个通路和一个组（i）第一个额外的通孔和第二个额外的通孔（ii）第一个额外的通孔加上一些足够电迁移问题的通孔，考虑到第一个额外的通孔，考虑到压力迁移问题，仍然有效通过数字大于零。

48. 发明申请

US20130326446A1 TECHNIQUES FOR CHECKING COMPUTER-AIDED DESIGN LAYERS OF A DEVICE TO REDUCE THE OCCURRENCE OF MISSING DECK RULES 有权
标题翻译：检查设备的计算机辅助设计层的技术，以减少错误的规则规则的发生
公开(公告)号：US20130326446A1
公开(公告)日：2013-12-05
申请号：US13484022
申请日：2012-05-30
申请人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
发明人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A technique for computer-aided design layer checking of an integrated circuit design includes generating a representation of a device (e.g., a parameterized cell). Computer-aided design (CAD) layers are sequentially removed from the parameterized cell and a determination is made as to whether expected errors are detected or missed by an associated deck. The associated deck is then modified to detect the expected errors that are missed.
摘要翻译：用于集成电路设计的计算机辅助设计层检查的技术包括生成设备（例如，参数化单元）的表示。计算机辅助设计（CAD）层从参数化的单元中顺序地移除，并且确定是否由相关联的卡座检测到或错过预期的错误。然后修改相关甲板以检测错过的预期错误。

49. 发明申请

US20130105986A1 SEMICONDUCTOR DEVICE WITH VIAS ON A BRIDGE CONNECTING TWO BUSES 有权
标题翻译：具有VIAS的半导体器件连接两条总线
公开(公告)号：US20130105986A1
公开(公告)日：2013-05-02
申请号：US13285073
申请日：2011-10-31
申请人： DOUGLAS M. REBER , Mehul D. Shroff , Edward O. Travis
发明人： DOUGLAS M. REBER , Mehul D. Shroff , Edward O. Travis
IPC分类号： H01L23/48 , G06F17/50
CPC分类号： G06F13/4027 , G06F17/5077 , H01L23/5221 , H01L23/528 , H01L23/5283 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses. At least N plus one (N+1) vias are coupled between every one of the conductive bridges and a respective feature in an integrated circuit when: (1) a width of the respective conductive bridge is less than a width of each of the at least two portions of the at least one of the conductive buses to which the respective conductive bridge is coupled, and (2) a distance along the respective conductive bridge and at least one of the vias is less than a critical distance. N is a number of conductive couplings between the respective one of the conductive bridges and the at least one of the conductive buses.
摘要翻译：半导体器件包括导电总线和导电桥。相应的导电桥与至少一个导电总线的至少两个部分导电耦合。当以下情况下，至少N + 1个（N + 1）通孔耦合在每个导电桥和集成电路中的相应特征之间：（1）相应导电桥的宽度小于每个导体桥的宽度所述至少一个导电总线的至少一个导体总线的至少两个部分相互连接，并且（2）沿相应导电桥和至少一个通孔的距离小于临界距离。 N是在相应的一个导电桥和至少一个导电总线之间的多个导电耦合。

50. 发明授权

US5814893A Semiconductor device having a bond pad 失效
标题翻译：具有接合焊盘的半导体器件
公开(公告)号：US5814893A
公开(公告)日：1998-09-29
申请号：US799925
申请日：1997-02-13
申请人： Ting-Chen Hsu , Edward O. Travis , Clifford M. Howard , Stephen G. Jamison
发明人： Ting-Chen Hsu , Edward O. Travis , Clifford M. Howard , Stephen G. Jamison
IPC分类号： H01L21/20 , H01L21/316 , H01L21/318 , H01L21/60 , H01L23/485 , H01L23/532 , H01L23/48 , H01L23/52
CPC分类号： H01L24/48 , H01L21/2007 , H01L23/53223 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05187 , H01L2224/05624 , H01L2224/05647 , H01L2224/45124 , H01L2224/4807 , H01L2224/48458 , H01L2224/4847 , H01L2224/48724 , H01L2224/48747 , H01L24/45 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , Y10S438/958
摘要： Bond pads (394, 106) and bond pad openings (62, 108) are formed such that the bond pad openings (62, 108) are asymmetric to the conductive sections (398, 106) of the bond pads (394, 106). If the bond pads are more likely to lift from the scribe line side of the bond pad (394, 106), the bond pad openings (62, 108) are formed such that the passivation layer (52) overlies more of the conductive section (398, 106) near the scribe line (40). If the bond pads (394, 106) are more likely to lift from the other side, the passivation layer (52) overlies more of the other side of the conductive section (398, 106). In addition to reducing the risk of lifting, contamination problems should also be reduced.
摘要翻译：形成接合焊盘（394,106）和接合焊盘开口（62,108），使得接合焊盘开口（62,108）与焊盘（394,106）的导电部分（398,106）不对称。如果接合焊盘更可能从接合焊盘（394,106）的划线侧提升，则形成接合焊盘开口（62,108），使得钝化层（52）覆盖导电部分 398,106）在划线（40）附近。如果接合焊盘（394,106）更可能从另一侧抬起，则钝化层（52）覆盖在导电部分（398,106）的另一侧的更多侧。除了降低起重风险外，还应降低污染问题。

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