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41. 发明授权

US4578800A Synchronization circuit for a Viterbi decoder 失效
标题翻译：维特比解码器同步电路
公开(公告)号：US4578800A
公开(公告)日：1986-03-25
申请号：US511503
申请日：1983-07-06
申请人： Yutaka Yasuda , Yasuo Hirata , Shuji Murakami , Katsuhiro Nakamura , Yukitsuna Furuya
发明人： Yutaka Yasuda , Yasuo Hirata , Shuji Murakami , Katsuhiro Nakamura , Yukitsuna Furuya
IPC分类号： H03M13/33 , H04L7/00 , H04L7/02 , H04L7/04
CPC分类号： H03M13/33 , H04L7/0062
摘要： A Viterbi decoder synchronization circuit comprises a phase shifter for introducing a variable amount of delay time to a received bit stream of convolutional codes in response to a control signal applied thereto with respect to a word synchronization signal which is derived from the bit stream. A first detector detects maximum and minimum metric values of the Viterbi decoder. A second detector detects the difference between the detected maximum and minimum metric values for coupling to an integrator. The output of the integrator is applied to a third detector which detects when the integrator output reaches a value indicative of a word-in-sync or word-out-of-sync condition. A phase shift signal is generated in response to an output signal from the third detector and applied to the phase shifter as the control signal.
摘要翻译：维特比解码器同步电路包括一个移相器，用于响应于从比特流导出的字同步信号施加的控制信号，将可变量的延迟时间引入到所接收的卷积码比特流中。第一检测器检测维特比解码器的最大和最小度量值。第二检测器检测检测到的与积分器耦合的最大和最小度量值之间的差异。积分器的输出被施加到第三检测器，该第三检测器检测积分器输出何时达到指示同步字或字不同步条件的值。响应于来自第三检测器的输出信号产生相移信号，并将其作为控制信号施加到移相器。

42. 发明授权

US4527279A Synchronization circuit for a Viterbi decoder 失效
标题翻译：维特比解码器同步电路
公开(公告)号：US4527279A
公开(公告)日：1985-07-02
申请号：US511774
申请日：1983-07-06
申请人： Yutaka Yasuda , Yasuo Hirata , Shuji Murakami , Katsuhiro Nakamura , Yukitsuna Furuya
发明人： Yutaka Yasuda , Yasuo Hirata , Shuji Murakami , Katsuhiro Nakamura , Yukitsuna Furuya
IPC分类号： H03M13/33 , H04L7/04
CPC分类号： H03M13/33
摘要： A Viterbi decoder synchronization circuit comprises a circuit that derives a word synchronization signal from a received bit stream of convolutional codes. A first detector detects a maximum of metric values derived from the Viterbi decoder at different locations in time. A memory is provided for storing therein the address codes derived at different times and the maximum metric values detected by the first detector. A second detector is connected to the memory for detecting the presence of a path between the states addressed by the address codes stored in the memory. An integrator is connected to the second detector to integrate its output signal. To the integrator is connected a third detector which detects when the integrator output reaches a value indicative of one of word-in-sync and word-out-of-sync conditions of the Viterbi decoder. A phase shift signal is generated in response to an output signal from the third detector and applied to a phase shifter to introduce a delay time to the bit stream.
摘要翻译：维特比解码器同步电路包括从接收到的卷积码的比特流导出字同步信号的电路。第一检测器在不同的时间点检测从维特比解码器导出的度量值的最大值。提供存储器，用于在其中存储在不同时间导出的地址码和由第一检测器检测的最大度量值。第二检测器连接到存储器，用于检测由存储在存储器中的地址码寻址的状态之间的路径的存在。积分器连接到第二检测器以整合其输出信号。连接到积分器的第三检测器，其检测积分器输出何时达到表示维特比解码器的同步字和同步字的其中一个的值。响应于来自第三检测器的输出信号产生相移信号，并将其应用于移相器以向该比特流引入延迟时间。

43. 发明申请

US20120096107A1 HOME APPLIANCE MANAGING SYSTEM 有权
标题翻译：家用电器管理系统
公开(公告)号：US20120096107A1
公开(公告)日：2012-04-19
申请号：US13319954
申请日：2010-05-11
申请人： Tomoyuki Hatanaka , Osamu Sekine , Shuji Murakami , Hiroyasu Nakanishi
发明人： Tomoyuki Hatanaka , Osamu Sekine , Shuji Murakami , Hiroyasu Nakanishi
IPC分类号： G06F15/167
CPC分类号： H04L12/2823 , H04L41/00
摘要： The home appliance managing system includes a plurality of central managing devices and a center server. The center server is connected to the plurality of the central managing devices, and stores plural data used at home appliances. When the central managing device stores predetermined data requested by the home appliance, the central managing device sends the predetermined data to the home appliance. When the central managing device does not store the predetermined data, the central managing device requests the predetermined data from the center server. The center server sends the predetermined data to the central managing device in response to the request from the central managing device. The central managing device sends the predetermined data received from the center server to the home appliance and stores the same data. The center server selects the cache data from the plural data on the basis of the data previously sent to the central managing device, and sends the cache data to the central managing device. The central managing device stores the cache data received from the center server.
摘要翻译：家用电器管理系统包括多个中央管理装置和中央服务器。中心服务器连接到多个中央管理设备，并且存储在家用电器中使用的多个数据。当中央管理装置存储家用电器要求的预定数据时，中央管理装置将预定数据发送给家用电器。当中央管理设备不存储预定数据时，中央管理设备从中心服务器请求预定数据。响应于来自中央管理设备的请求，中心服务器将预定数据发送给中央管理设备。中央管理设备将从中心服务器接收的预定数据发送到家用电器并存储相同的数据。中心服务器根据先前发送到中央管理设备的数据，从多个数据中选择缓存数据，并将高速缓存数据发送到中央管理设备。中央管理设备存储从中央服务器接收的高速缓存数据。

44. 发明申请

US20080240736A1 Inter-Symbol Interference-Suppressed Colorless DPSK Demodulation 审中-公开
标题翻译：符号间干扰抑制无色DPSK解调
公开(公告)号：US20080240736A1
公开(公告)日：2008-10-02
申请号：US11692432
申请日：2007-03-28
申请人： Philip Nan Ji , Lei Xu , Ting Wang , Shuji Murakami , Tsutomu Tajima , Yutaka Yano
发明人： Philip Nan Ji , Lei Xu , Ting Wang , Shuji Murakami , Tsutomu Tajima , Yutaka Yano
IPC分类号： H04B10/06
CPC分类号： H04B10/677
摘要： An optical device includes an interferometer for a received optical differential phase shift keying DPSK signal, and an equalizer integrated with the interferometer in a manner for reducing from optical filtering effects an interference by signal bits of the DPSK signal with signal bits of a contiguous DPSK signal. The interferometer is a Michelson delay interferometer type, but can also be a Mach-Zehnder delay interferometer type on fiber, waveguide or other optical structure. The equalizer is a Fabry-Perot type equalizer, but can be a ring resonator type or a fiber based equalizer.
摘要翻译：光学装置包括用于接收的光学差分相移键控DPSK信号的干涉仪，以及与干涉仪集成的均衡器，以减少光学滤波的方式，利用DPSK信号的信号位与相邻DPSK信号的信号位的干扰。干涉仪是迈克尔逊延迟干涉仪型号，但也可以是光纤，波导或其他光学结构上的马赫 - 曾德延迟干涉仪。均衡器是法布里 - 珀罗型均衡器，但可以是环形谐振器型或基于光纤的均衡器。

45. 发明申请

US20070179243A1 Optical element 审中-公开
标题翻译：光学元件
公开(公告)号：US20070179243A1
公开(公告)日：2007-08-02
申请号：US11698908
申请日：2007-01-29
申请人： Daisuke Watanabe , Shuji Murakami
发明人： Daisuke Watanabe , Shuji Murakami
IPC分类号： C08L83/04
CPC分类号： G02B3/00 , C08K3/013 , G02B5/1876 , G11B7/1353 , G11B7/1374 , G11B7/22 , G11B2007/0006
摘要： Disclosed is an optical element that has high quality with respect to heat resistance and light resistance, as well as high quality with respect to light transmittance. The optical element includes a thermosetting resin and fine particles, and difference between refractive index of the thermosetting resin n1 and refractive index of the fine particles n2, |n1−n2| satisfies a condition of 0≦|n1−n2|≦0.1.
摘要翻译：公开了一种相对于耐热性和耐光性而具有高品质的光学元件以及相对于透光率的高品质。光学元件包括热固性树脂和细颗粒，热固性树脂n1的折射率和细颗粒的折射率n2，| n1-n2 | 满足条件0 <= | n1-n2 | <= 0.1。

46. 发明申请

US20060280099A1 Optical element and optical pickup apparatus 审中-公开
标题翻译：光学元件和光学拾取装置
公开(公告)号：US20060280099A1
公开(公告)日：2006-12-14
申请号：US11438341
申请日：2006-05-23
申请人： Shuji Murakami
发明人： Shuji Murakami
IPC分类号： G11B7/135
CPC分类号： G11B7/1374 , C08F232/08 , G11B7/121 , G11B7/1353
摘要： An object of the invention is to suppress adherence of dust or stain due to the environment and provide an optical element that can maintain optical characteristic for a long period of time, and achieve high durability and reliability. It is also another object of the invention to provide an optical pickup apparatus with good pickup characteristic, using the optical element. Disclosed is an optical element, including: plastic compound, wherein charging characteristic of the optical element is not less than +2 kV and not more than +15 kV, and transmission of the optical element for a light flux having a wavelength of 405 nm is not less than 85%.
摘要翻译：本发明的目的是抑制由于环境而引起的灰尘或污渍的粘附，并且提供能够长时间保持光学特性的光学元件，并且实现高耐久性和可靠性。本发明的另一个目的是提供使用光学元件的具有良好拾取特性的光学拾取装置。公开了一种光学元件，包括：塑料复合物，其中光学元件的充电特性不小于+2kV且不大于+ 15kV，并且用于波长为405nm的光通量的光学元件的透射是不低于85％。

47. 发明授权

US06815157B2 Silver halide emulsion and silver halide photographic material 失效
标题翻译：卤化银乳剂和卤化银照相材料
公开(公告)号：US06815157B2
公开(公告)日：2004-11-09
申请号：US10756415
申请日：2004-01-14
申请人： Toshiya Kondo , Shuji Murakami , Koichiro Kuroda
发明人： Toshiya Kondo , Shuji Murakami , Koichiro Kuroda
IPC分类号： G03C109
CPC分类号： G03C1/346 , G03C1/035 , G03C1/09 , G03C1/10 , G03C7/30 , G03C2001/03517 , G03C2001/093
摘要： A silver halide emulsion comprising silver halide grains containing at least 90 mol % chloride, 0.02 to 5.0 mol % bromide and 0 to 2.0 mol % iodide, which is prepared by a process comprising (i) forming a silver halide grain emulsion, (ii) subjecting the silver halide emulsion to desalting and (iii) subjecting the desalted silver halide emulsion to chemical sensitization by adding a chemical sensitizer, wherein in the step (iii), at least one compound represented by the following formula (1) to (4) is added before adding a chemical sensitizer and at least one compound represented by the following formula (1) to (4) is further added after adding a chemical sensitizer
摘要翻译：一种卤化银乳剂，其包含含有至少90mol％氯化物，0.02-5.0mol％溴化物和0-2.0mol％碘化物的卤化银颗粒，其通过以下方法制备，所述方法包括（i）形成卤化银颗粒乳剂，（ii）使所述卤化银乳剂脱盐，和（iii）通过添加化学增感剂对脱盐的卤化银乳剂进行化学增感，其中在步骤（iii）中，至少一种由下式（1）至（4）表示的化合物，在添加化学增感剂之前加入至少一种由下式（1）至（4）表示的化合物，在加入化学敏化剂

48. 发明授权

US5475638A Static random access memory device having a single bit line configuration 失效
标题翻译：具有单位线配置的静态随机存取存储器件
公开(公告)号：US5475638A
公开(公告)日：1995-12-12
申请号：US25470
申请日：1993-03-03
申请人： Kenji Anami , Toshihiko Hirose , Shuji Murakami , Kojiro Yuzuriha , Tadato Yamagata
发明人： Kenji Anami , Toshihiko Hirose , Shuji Murakami , Kojiro Yuzuriha , Tadato Yamagata
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C11/40
CPC分类号： H01L27/11 , G11C11/412 , G11C11/418 , G11C11/419 , H01L27/1108
摘要： A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.
摘要翻译：公开了具有单个位线配置的静态随机存取存储器（SRAM）。一个存储单元包括串联连接在数据存储电路1和单个位线BL之间的存取栅极晶体管Q5，Q6。在写入操作中，晶体管Q5，Q6的栅电极通过X字线升压电路7和Y字线升压电路8升压到超过电源电压的电平，以使数据存储电路处于不稳定的数据存储状态在由行地址信号和列地址信号选择的存储单元中。仅在期望的存储单元中执行数据写入，并且防止对其它存储单元的错误数据写入。

49. 发明授权

US5471427A Circuit for repairing defective bit in semiconductor memory device and repairing method 失效
标题翻译：用于修复半导体存储器件中的有缺陷的位的电路和修复方法
公开(公告)号：US5471427A
公开(公告)日：1995-11-28
申请号：US262755
申请日：1994-06-20
申请人： Shuji Murakami , Tomohisa Wada , Kenji Anami
发明人： Shuji Murakami , Tomohisa Wada , Kenji Anami
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/848
摘要： A circuit for repairing a defective memory cell is provided between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line. The repair circuit occupies a reduced area of a chip because of no spare decoder and nor program circuit and it carries out a reliable and fast memory repair because of the reduced number of the fuse elements to be blown off.
摘要翻译：在行或列解码器和存储单元阵列之间提供用于修复有缺陷的存储单元的电路。当解码器具有n条输出线时，存储单元阵列至少包括（N + 1）行或列线，其中n是整数。修复电路包括用于将解码器的输出线连接到行或列线的连接电路，以及用于限定连接电路的连接的电路。连接电路包括n个开关元件，每个开关元件可操作以将解码器的一个输出线连接到至少两个行或列线。定义电路定义每个开关元件的连接路径，使得解码器的输出线与连续有缺陷的存储器单元的行或列线排除在连续定位的行或列之间一一对应。定义电路包括设置在工作电压源和接地线之间的一系列激光可编程保险丝元件。由于没有备用解码器和编程电路，修复电路占用了芯片的减少面积，并且由于要被熔断的熔丝元件的数量减少，所以它进行可靠且快速的存储器修复。

50. 发明授权

US5379258A Circuit for repairing defective bit in semiconductor memory device and repairing method 失效
标题翻译：用于修复半导体存储器件中的有缺陷的位的电路和修复方法
公开(公告)号：US5379258A
公开(公告)日：1995-01-03
申请号：US828254
申请日：1992-01-30
申请人： Shuji Murakami , Tomohisa Wada , Kenji Anami
发明人： Shuji Murakami , Tomohisa Wada , Kenji Anami
IPC分类号： G11C11/401 , G11C11/407 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/848 , G11C29/70
摘要： A circuit for repairing a defective memory cell between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line. The repair circuit occupies a reduced area of a chip because of no spare decoder and no program circuit and it carries out a reliable and fast memory repair because of the reduced number of the fuse elements to be blown off.
摘要翻译：一种用于修复行或列解码器和存储单元阵列之间的有缺陷的存储单元的电路。当解码器具有n条输出线时，存储单元阵列至少包括（N + 1）行或列线，其中n是整数。修复电路包括用于将解码器的输出线连接到行或列线的连接电路和用于限定连接电路的连接的电路。连接电路包括n个开关元件，每个开关元件可操作以将解码器的一个输出线连接到至少两个行或列线。定义电路定义每个开关元件的连接路径，使得解码器的输出线与连续有缺陷的存储器单元的行或列线排除在连续定位的行或列之间一一对应。定义电路包括设置在工作电压源和接地线之间的一系列激光可编程保险丝元件。由于没有备用解码器和编程电路，修复电路占用了芯片的减少面积，并且由于要被熔断的熔丝元件的数量减少，所以其执行可靠且快速的存储器修复。

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