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41. 发明申请

US20050239218A1 Ferroelectric capacitor having a substantially planar dielectric layer and a method of manufacture therefor 有权
标题翻译：具有基本上平面的电介质层的铁电电容器及其制造方法
公开(公告)号：US20050239218A1
公开(公告)日：2005-10-27
申请号：US10829053
申请日：2004-04-21
申请人： Sanjeev Aggarwal , Kelly Taylor , Lindsey Hall , Satyavolu Rao
发明人： Sanjeev Aggarwal , Kelly Taylor , Lindsey Hall , Satyavolu Rao
IPC分类号： H01L21/00 , H01L21/02 , H01L21/20 , H01L21/3105 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11585 , H01L21/31053 , H01L27/11502 , H01L27/1159 , H01L28/55
摘要： The present invention provides a ferroelectric capacitor, a method of manufacture therefor, and a method of manufacturing a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (100), among other elements, includes a substantially planar ferroelectric dielectric layer (165) located over a first electrode layer (160), wherein the substantially planar ferroelectric dielectric layer (165) has an average surface roughness of less than about 4 nm. The ferroelectric capacitor (100) further includes a second electrode layer (170) located over the substantially planar ferroelectric dielectric layer (165).
摘要翻译：本发明提供一种铁电电容器及其制造方法，以及制造铁电随机存取存储器（FeRAM）器件的方法。除了其他元件之外，铁电电容器（100）包括位于第一电极层（160）上方的基本平坦的铁电介质层（165），其中基本上平坦的铁电介质层（165）的平均表面粗糙度小于约 4nm。铁电电容器（100）还包括位于基本上平坦的铁电介质层（165）上方的第二电极层（170）。

42. 发明授权

US06610549B1 Amorphous barrier layer in a ferroelectric memory cell 失效
标题翻译：铁电存储单元中的无定形阻挡层
公开(公告)号：US06610549B1
公开(公告)日：2003-08-26
申请号：US09709051
申请日：2000-11-10
申请人： Sanjeev Aggarwal , Ramamoorthy Ramesh
发明人： Sanjeev Aggarwal , Ramamoorthy Ramesh
IPC分类号： H01L218239
CPC分类号： H01L21/7687 , H01L27/11502 , H01L28/55 , H01L28/75
摘要： A ferroelectric cell, particularly one integrated on a silicon substrate, comprising an amorphous barrier layer interposed between the ferroelectric stack and the silicon. Preferably, the ferroelectric stack includes conductive metal oxide electrodes sandwiching the ferroelectric layer. The metal oxide may act as a templating layer to crystallographically orient the ferroelectric layer. Alternatively, the electrodes and ferroelectric layer may be polycrystalline. The amorphous barrier layer may be composed of an intermetallic alloy, such as Ti3Al, a metal-metalloid, such as Pd—Si, a combination of early and later transition metals, such as Ti—Ni, and other related compound metal systems, such as (Ti, Zr)—Be, that form amorphous metals.
摘要翻译：特别是集成在硅衬底上的铁电电池，包括介于铁电堆和硅之间的无定形阻挡层。优选地，铁电体层包括夹着铁电体层的导电金属氧化物电极。金属氧化物可以用作模板层以使铁电层晶体取向。或者，电极和铁电层可以是多晶的。无定形阻挡层可以由诸如Ti 3 Al的金属间合金，诸如Pd-Si的金属 - 准金属，诸如Ti-Ni的早期和稍后的过渡金属的组合以及其它相关的复合金属体系组成，例如作为（Ti，Zr）-Be，形成无定形金属。

43. 发明授权

US06528386B1 Protection of tungsten alignment mark for FeRAM processing 有权
标题翻译：保护钨对准标记用于FeRAM处理
公开(公告)号：US06528386B1
公开(公告)日：2003-03-04
申请号：US10097919
申请日：2002-03-13
申请人： Scott R. Summerfelt , Luigi Colombo , Stephen R. Gilbert , Theodore S. Moise, IV , Sanjeev Aggarwal
发明人： Scott R. Summerfelt , Luigi Colombo , Stephen R. Gilbert , Theodore S. Moise, IV , Sanjeev Aggarwal
IPC分类号： H01L2176
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom electrode layer, a protective film is formed on the sidewalls of the capacitor stack structure in order to protect the dielectric material from conductive contaminants associated with a subsequent patterning of the bottom electrode layer.
摘要翻译：公开了一种制造铁电电容器的方法。该方法包括图案化顶部电极层和电介质层以形成具有与其相关联的侧壁的电容器堆叠结构。在图形化底部电极层之前，在电容器堆叠结构的侧壁上形成保护膜，以保护电介质材料免受与随后的底部电极层的图案化有关的导电污染物的影响。

44. 发明授权

US6115281A Methods and structures to cure the effects of hydrogen annealing on ferroelectric capacitors 失效
标题翻译：固化氢退火对铁电电容器的影响的方法和结构
公开(公告)号：US6115281A
公开(公告)日：2000-09-05
申请号：US151903
申请日：1998-09-11
申请人： Sanjeev Aggarwal , Scott Robert Perusse , Ramamoorthy Ramesh
发明人： Sanjeev Aggarwal , Scott Robert Perusse , Ramamoorthy Ramesh
IPC分类号： H01L21/02 , H04L12/26 , H04L12/56 , H04Q11/04 , G11C11/22
CPC分类号： H04Q11/0478 , H01L28/55 , H01L28/75 , H04L49/3081 , H04L2012/5636
摘要： A ferroelectric memory cell integrated with silicon circuitry which require a forming-gas anneal of the silicon circuitry after the ferroelectric stack has been formed. The ferroelectric layer may have a composition such that there is no space in the lattice of the ferroelectric phase to accommodate atomic hydrogen or have a composition with a Curie temperature below the temperature of the forming-gas anneal. Preferably, there is no upper platinum electrode, or it is deposited after the forming-gas anneal. A metal-oxide upper electrode serves as barrier to the forming-gas anneal, and an intermetallic layer positioned above the ferroelectric stack serves as an even better barrier. Forming-gas damage to the ferroelectric stack can be removed by a recovery anneal in a hydrogen-free environment, preferably performed at a temperature above the Curie temperature.
摘要翻译：与硅电路集成的铁电存储单元，其在形成铁电叠层之后需要硅电路的成形气体退火。铁电层可以具有使铁电相的晶格中没有空间以适应原子氢或具有低于成形气体退火温度的居里温度的组成的组成。优选地，不存在上铂电极，或者在成形气体退火之后沉积。金属氧化物上电极用作形成气体退火的阻挡层，并且位于铁电堆叠上方的金属间层用作更好的屏障。铁电堆的形成气体损伤可以通过在无氢环境中的回收退火来去除，优选在高于居里温度的温度下进行。

45. 发明授权

US08685756B2 Method for manufacturing and magnetic devices having double tunnel barriers 有权
标题翻译：具有双层隧道屏障的制造方法和磁性装置
公开(公告)号：US08685756B2
公开(公告)日：2014-04-01
申请号：US13250361
申请日：2011-09-30
申请人： Sanjeev Aggarwal , Kerry Nagel , Jason Janesky
发明人： Sanjeev Aggarwal , Kerry Nagel , Jason Janesky
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/10
摘要： A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer.
摘要翻译：双隧道屏障磁性元件具有位于第一和第二隧道屏障之间的自由磁性层和位于第二隧道屏障上的电极。两步蚀刻工艺允许在第一次蚀刻之后在电极的侧壁上形成封装材料，并且在进行第二蚀刻以去除自由层的一部分时防止第一隧道势垒的损坏。

46. 发明授权

US08451064B2 Voltage-controlled oscillator module having adjustable oscillator gain and related operating methods 有权
标题翻译：压控振荡器模块具有可调节的振荡器增益和相关的操作方法
公开(公告)号：US08451064B2
公开(公告)日：2013-05-28
申请号：US12900163
申请日：2010-10-07
申请人： Sanjeev Maheshwari , Emerson Fang , Sanjeev Aggarwal
发明人： Sanjeev Maheshwari , Emerson Fang , Sanjeev Aggarwal
IPC分类号： H03L7/18
CPC分类号： H03L7/0998
摘要： Apparatus and methods are provided for oscillators having adjustable gain. An exemplary oscillator module comprises a first node for a first voltage, a control node for a control signal, and oscillator circuitry coupled to the first node and the control node. The oscillator circuitry generates an output signal with a first oscillation frequency based on the first voltage, and in response to the control signal being asserted, the oscillator circuitry generates the output signal with a second oscillation frequency based on the first voltage. The second oscillation frequency is greater than the first oscillation frequency.
摘要翻译：提供了具有可调增益的振荡器的装置和方法。示例性振荡器模块包括用于第一电压的第一节点，用于控制信号的控制节点和耦合到第一节点和控制节点的振荡器电路。振荡器电路基于第一电压产生具有第一振荡频率的输出信号，并且响应于控制信号被断言，振荡器电路基于第一电压产生具有第二振荡频率的输出信号。第二振荡频率大于第一振荡频率。

47. 发明申请

US20130082339A1 METHOD FOR MANUFACTURING AND MAGNETIC DEVICES HAVING DOUBLE TUNNEL BARRIERS 有权
标题翻译：具有双通道障碍物的制造方法和磁性装置
公开(公告)号：US20130082339A1
公开(公告)日：2013-04-04
申请号：US13250361
申请日：2011-09-30
申请人： Sanjeev Aggarwal , Kerry Nagel , Jason Janesky
发明人： Sanjeev Aggarwal , Kerry Nagel , Jason Janesky
IPC分类号： H01L29/82 , H01L21/8246
CPC分类号： H01L43/12 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/10
摘要： A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer.
摘要翻译：双隧道屏障磁性元件具有位于第一和第二隧道屏障之间的自由磁性层和位于第二隧道屏障上的电极。两步蚀刻工艺允许在第一次蚀刻之后在电极的侧壁上形成封装材料，并且在进行第二蚀刻以去除自由层的一部分时防止第一隧道势垒的损坏。

48. 发明授权

US08211794B2 Properties of metallic copper diffusion barriers through silicon surface treatments 有权
标题翻译：通过硅表面处理的金属铜扩散阻挡层的性能
公开(公告)号：US08211794B2
公开(公告)日：2012-07-03
申请号：US11753926
申请日：2007-05-25
申请人： Valli Arunachalam , Satyavolu Srinivas Papa Rao , Sanjeev Aggarwal , Stephan Grunow
发明人： Valli Arunachalam , Satyavolu Srinivas Papa Rao , Sanjeev Aggarwal , Stephan Grunow
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76826 , H01L21/76831 , H01L21/76843 , H01L21/76846 , H01L21/76856 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of fabricating a diffusion barrier can include providing a dielectric layer, forming a first silicon enriched layer over the dielectric layer by exposing the dielectric layer to a silicon-containing ambient, and forming a barrier layer over the first silicon enriched layer.
摘要翻译：根据本发明，存在扩散阻挡层，集成电路和半导体器件及其制造方法。制造扩散阻挡层的方法可以包括提供电介质层，通过将电介质层暴露于含硅环境，在介电层上形成第一富硅层，并在第一富硅层上形成阻挡层。

49. 发明申请

US20090085058A1 ELECTRONIC DEVICE INCLUDING A MAGNETO-RESISTIVE MEMORY DEVICE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 有权
标题翻译：包括磁电阻记忆体装置的电子装置和形成电子装置的方法
公开(公告)号：US20090085058A1
公开(公告)日：2009-04-02
申请号：US11864409
申请日：2007-09-28
申请人： Phillip G. Mather , Sanjeev Aggarwal , Brian R. Butcher , Renu W. Dave , Frederick B. Mancoff , Nicholas D. Rizzo
发明人： Phillip G. Mather , Sanjeev Aggarwal , Brian R. Butcher , Renu W. Dave , Frederick B. Mancoff , Nicholas D. Rizzo
IPC分类号： H01L29/82 , H01L21/46
CPC分类号： H01L43/08 , B82Y10/00 , B82Y25/00 , G11C11/161 , H01L43/12
摘要： A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.
摘要翻译：形成电子器件的工艺可以包括形成包括隧道势垒层的堆叠。隧道阻挡层可以具有大于化学计量比的金属原子与氧原子的比例，其中该比率具有特定值。该方法还可以包括形成具有能够吸收氧的组成的吸气层，以及在吸气层上沉积绝缘层。该方法还可以包括将绝缘层暴露于至少约60℃的温度。在一个实施方案中，在这种曝光之后，将一部分吸气层转化为绝缘材料。在另一个实施例中，电子设备可以包括磁性隧道结和位于另一绝缘层的开口内的相邻绝缘层。

50. 发明授权

US07153706B2 Ferroelectric capacitor having a substantially planar dielectric layer and a method of manufacture therefor 有权
标题翻译：具有基本上平面的电介质层的铁电电容器及其制造方法
公开(公告)号：US07153706B2
公开(公告)日：2006-12-26
申请号：US10829053
申请日：2004-04-21
申请人： Sanjeev Aggarwal , Kelly J. Taylor , Lindsey Hall , Satyavolu Srinivas Papa Rao
发明人： Sanjeev Aggarwal , Kelly J. Taylor , Lindsey Hall , Satyavolu Srinivas Papa Rao
IPC分类号： H01L21/00
CPC分类号： H01L27/11585 , H01L21/31053 , H01L27/11502 , H01L27/1159 , H01L28/55
摘要： The present invention provides a ferroelectric capacitor, a method of manufacture therefor, and a method of manufacturing a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (100), among other elements, includes a substantially planar ferroelectric dielectric layer (165) located over a first electrode layer (160), wherein the substantially planar ferroelectric dielectric layer (165) has an average surface roughness of less than about 4 nm. The ferroelectric capacitor (100) further includes a second electrode layer (170) located over the substantially planar ferroelectric dielectric layer (165).
摘要翻译：本发明提供一种铁电电容器及其制造方法，以及制造铁电随机存取存储器（FeRAM）器件的方法。除了其他元件之外，铁电电容器（100）包括位于第一电极层（160）上方的基本平坦的铁电介质层（165），其中基本上平坦的铁电介质层（165）的平均表面粗糙度小于约 4nm。铁电电容器（100）还包括位于基本上平坦的铁电介质层（165）上方的第二电极层（170）。

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