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41. 发明授权

US08835980B2 Semiconductor wafer, photoelectric conversion device, method of producing semiconductor wafer, and method of producing photoelectric conversion device 有权
标题翻译：半导体晶片，光电转换元件，半导体晶片的制造方法以及光电转换元件的制造方法
公开(公告)号：US08835980B2
公开(公告)日：2014-09-16
申请号：US13310614
申请日：2011-12-02
申请人： Masahiko Hata , Taro Itatani
发明人： Masahiko Hata , Taro Itatani
IPC分类号： H01L31/0264 , H01L31/0392 , H01L31/052 , H01L31/18 , H01L31/076 , H01L27/142
CPC分类号： H01L31/0522 , H01L27/142 , H01L31/028 , H01L31/03046 , H01L31/0392 , H01L31/0475 , H01L31/0543 , H01L31/0687 , H01L31/076 , H01L31/077 , H01L31/1852 , Y02E10/52 , Y02E10/544 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： Provided is a semiconductor wafer including: a base wafer containing silicon; an inhibitor that has been formed on the base wafer, has an aperture in which a surface of the base wafer is exposed, and inhibits crystal growth; and a light-absorptive structure that has been formed inside the aperture in contact with a surface of the base wafer exposed inside the aperture, where the light-absorptive structure includes a first semiconductor and a second semiconductor.
摘要翻译：提供一种半导体晶片，其包括：含有硅的基底晶片; 已经形成在基底晶片上的抑制剂具有露出基底晶片的表面的孔，并抑制晶体生长; 以及已经形成在所述孔内的与所述孔内露出的所述基底晶片的表面接触的光吸收结构，其中所述光吸收结构包括第一半导体和第二半导体。

42. 发明授权

US08686472B2 Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate 失效
标题翻译：半导体衬底，电子器件和半导体衬底的制造方法
公开(公告)号：US08686472B2
公开(公告)日：2014-04-01
申请号：US13122124
申请日：2009-10-01
申请人： Masahiko Hata
发明人： Masahiko Hata
IPC分类号： H01L21/02
CPC分类号： H01L21/8252 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02461 , H01L21/02463 , H01L21/02538 , H01L21/02551 , H01L21/02645 , H01L21/02647 , H01L21/8258 , H01L21/84 , H01L27/1203 , H01L29/20 , H01L29/66742 , H01L29/7371 , H01L29/78681
摘要： There is provided a semiconductor wafer including a base wafer, an insulating layer, and a Si crystal layer in the stated order. The semiconductor wafer further includes an inhibition layer that is provided on the Si crystal layer and has an opening penetrating therethrough to reach the Si crystal layer. The inhibition layer inhibiting crystal growth of a compound semiconductor. Furthermore, a seed crystal is provided within the opening, and a compound semiconductor has a lattice match or a pseudo lattice match with the seed crystal. There is also provided an electronic device includes a substrate, an insulating layer that is provided on the substrate, a Si crystal layer that is provided on the insulating layer, an inhibition layer that is provided on the Si crystal layer and has an opening penetrating therethrough to reach the Si crystal layer, where the inhibition layer inhibits crystal growth of a compound semiconductor, a seed crystal that is provided within the opening, a compound semiconductor that has a lattice match or a pseudo lattice match with the seed crystal, and a semiconductor device that is formed using the compound semiconductor.
摘要翻译：提供了以所述顺序包括基底晶片，绝缘层和Si晶体层的半导体晶片。半导体晶片还包括设置在Si晶体层上并具有贯穿其的开口以到达Si晶体层的抑制层。抑制层抑制化合物半导体的晶体生长。此外，在开口内设置晶种，化合物半导体与晶种具有晶格匹配或伪晶格匹配。还提供了一种电子器件，包括衬底，设置在衬底上的绝缘层，设置在绝缘层上的Si晶体层，设置在Si晶体层上并具有贯穿其的开口的抑制层到达Si晶体层，其中抑制层抑制化合物半导体的晶体生长，设置在开口内的晶种，具有晶格匹配或与晶种的伪晶格匹配的化合物半导体以及半导体使用化合物半导体形成的器件。

43. 发明授权

US08431459B2 Semiconductor wafer, semiconductor device, and method of manufacturing a semiconductor device 有权
标题翻译：半导体晶片，半导体器件以及半导体器件的制造方法
公开(公告)号：US08431459B2
公开(公告)日：2013-04-30
申请号：US12934233
申请日：2009-03-26
申请人： Mitsuru Takenaka , Shinichi Takagi , Masahiko Hata , Osamu Ichikawa
发明人： Mitsuru Takenaka , Shinichi Takagi , Masahiko Hata , Osamu Ichikawa
IPC分类号： H01L21/00
CPC分类号： H01L29/7787 , H01L21/28264 , H01L29/205 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/78648 , H01L29/78681
摘要： It is an objective of the present invention to form a favorable interface between an oxide layer and a group 3-5 compound semiconductor using a practical and simple method.Provided is a semiconductor wafer comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; and a second semiconductor layer that is formed to contact the first semiconductor layer, is a group 3-5 compound semiconductor layer that lattice matches or pseudo-lattice matches with InP, and can be selectively oxidized relative to the first semiconductor layer. Also provided is a semiconductor device comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; an oxide layer formed by selectively oxidizing, relative to the first semiconductor layer, at least a portion of a second semiconductor layer that is a group 3-5 compound formed to contact the first semiconductor layer and that lattice matches or pseudo-lattice matches with InP; and a control electrode that adds an electric field to a channel formed in the first semiconductor layer.
摘要翻译：本发明的目的是使用实用和简单的方法在氧化物层和3-5族化合物半导体之间形成良好的界面。提供了包括第一半导体层的半导体晶片，其是不含砷的组3-5化合物，并且晶格匹配或伪晶格与InP匹配; 和形成为与第一半导体层接触的第二半导体层是与InP晶格匹配或伪晶格匹配的组3-5化合物半导体层，并且可相对于第一半导体层选择性地氧化。还提供了一种半导体器件，其包括第一半导体层，其是不含砷的组3-5化合物，并且晶格匹配或伪晶格与InP匹配; 通过相对于第一半导体层选择性地氧化形成为与第一半导体层接触的组3-5化合物的第二半导体层的至少一部分，并且晶格匹配或伪晶格匹配的InP形成的氧化物层 ; 以及将电场与形成在第一半导体层中的沟道相加的控制电极。

44. 发明授权

US08395187B2 Compound semiconductor epitaxial substrate and manufacturing method thereof 有权
标题翻译：复合半导体外延基板及其制造方法
公开(公告)号：US08395187B2
公开(公告)日：2013-03-12
申请号：US13154624
申请日：2011-06-07
申请人： Tsuyoshi Nakano , Masahiko Hata
发明人： Tsuyoshi Nakano , Masahiko Hata
IPC分类号： H01L31/062 , H01L31/113 , H01L29/06 , H01L21/336
CPC分类号： H01L29/205
摘要： A compound semiconductor epitaxial substrate having a pseudomorphic high electron mobility field effect transistor structure including an InGaAs layer as a strained channel layer and an AlGaAs layer containing n type impurities as a front side electron-donating layer, wherein said substrate contains an InGaP layer in an orderly state on the front side of the above described InGaAs layer as the strained channel layer.
摘要翻译：一种具有假型高电子迁移率场效应晶体管结构的化合物半导体外延衬底，其包括作为应变沟道层的InGaAs层和含有n型杂质的AlGaAs层作为前侧电子给予层，其中所述衬底包含InGaP层，在作为应变通道层的上述InGaAs层的正面上有序地形成。

45. 发明申请

US20120032699A1 METHOD OF MEASURING ELECTRICAL CHARACTERISTICS OF SEMICONDUCTOR WAFER 有权
标题翻译：测量半导体滤波器电气特性的方法
公开(公告)号：US20120032699A1
公开(公告)日：2012-02-09
申请号：US13273781
申请日：2011-10-14
申请人： Noboru FUKUHARA , Masahiko Hata
发明人： Noboru FUKUHARA , Masahiko Hata
IPC分类号： G01R31/26
CPC分类号： G01R31/025 , G01R31/129
摘要： There is provided a method of measuring a leakage current or a dielectric breakdown voltage of a semiconductor wafer that has a base wafer and a buffer layer formed on the base wafer. The method includes providing, on the buffer layer, a plurality of electrodes including a hole injection electrode made of a material that injects a hole into the buffer layer when an electric field is applied thereto, measuring an electric current flowing through a pair of electrodes or a voltage between the electrodes when a voltage or an electric current is applied to the pair of electrodes, the electrodes including at least one hole injection electrode, and measuring a leakage current or a dielectric breakdown voltage caused by hole migration in the semiconductor wafer based on the current flowing through the pair of electrodes or the voltage generated between the pair of the electrodes.
摘要翻译：提供了一种测量半导体晶片的漏电流或介电击穿电压的方法，该半导体晶片具有形成在基底晶片上的基底晶片和缓冲层。该方法包括在缓冲层上设置多个电极，该多个电极包括由施加电场的空穴注入到缓冲层中的材料制成的空穴注入电极，测量流过一对电极的电流或当对一对电极施加电压或电流时，电极之间的电压，所述电极包括至少一个空穴注入电极，并且测量基于半导体晶片中的空穴迁移引起的漏电流或介电击穿电压，基于流过该对电极的电流或在一对电极之间产生的电压。

46. 发明申请

US20090166644A1 MONOLITHIC LIGHT EMITTING DEVICE AND DRIVING METHOD THEREFOR 有权
标题翻译：单光发光装置及其驱动方法
公开(公告)号：US20090166644A1
公开(公告)日：2009-07-02
申请号：US12293196
申请日：2007-03-22
申请人： Yuichi Hiroyama , Masahiko Hata , Yoshihiko Tsuchida
发明人： Yuichi Hiroyama , Masahiko Hata , Yoshihiko Tsuchida
IPC分类号： H01L33/00
CPC分类号： G02B6/0068 , G02B6/0025 , G02B6/0046 , G02B6/0051 , G02B6/0073 , H01L27/156 , H01L51/0007 , H01L51/5036
摘要： A monolithic light-emitting device and driving method therefore includes a plurality of light-emitting diodes, array-arranged monolithically on a single substrate. Thie light-emitting diodes include a pn junction-containing semiconductor material and a phosphor-containing layer passing light emitted from the semiconductor material, absorbing part, or whole of the light for conversion into light having a different wavelength. The array is constituted of a light-emitting diode group consisting of m (m≧2) pieces of the light-emitting diode, the light emitting diode group being constituted of N types (N≧2, providing N≦m) of light-emitting diodes, each having either one of preset N types of light-emitting spectrum patterns. An average light-emitting spectrum from the whole array can be changed by regulating a power supplied to the light-emitting diodes for each light-emitting diode group sorted according to the type of the light-emitting spectrum pattern.
摘要翻译：因此，单片发光器件和驱动方法包括多个发光二极管，其单个阵列地排列在单个衬底上。发光二极管包括含有pn结的半导体材料和通过从半导体材料发射的光的含磷光体层，吸收部分或全部光以转换成具有不同波长的光。该阵列由发光二极管的m（m≥2）个组成的发光二极管组构成，发光二极管组由N种（N> = 2，提供N

47. 发明申请

US20090031944A1 Method for producing compound semiconductor epitaxial substrate having PN junction 有权
标题翻译：具有PN结的化合物半导体外延基板的制造方法
公开(公告)号：US20090031944A1
公开(公告)日：2009-02-05
申请号：US11660936
申请日：2005-08-23
申请人： Kenji Kohiro , Kazumasa Ueda , Masahiko Hata
发明人： Kenji Kohiro , Kazumasa Ueda , Masahiko Hata
IPC分类号： C30B11/00
CPC分类号： H01L29/861 , H01L21/02395 , H01L21/02546 , H01L21/02579 , H01L21/02639 , H01L29/66136
摘要： Disclosed is a method for producing a compound semiconductor epitaxial substrate having a pn junction by selective growth which is characterized by using a base substrate having an average residual strain of not more than 1.0×10−5.
摘要翻译：公开了一种通过选择性生长制备具有pn结的化合物半导体外延基板的方法，其特征在于使用平均残余应变不大于1.0×10 -5的基底。

48. 发明申请

US20060249761A1 Semiconductor material for electronic device and semiconductor element using same 审中-公开
标题翻译：用于电子器件的半导体材料和使用其的半导体元件
公开(公告)号：US20060249761A1
公开(公告)日：2006-11-09
申请号：US10539008
申请日：2003-12-16
申请人： Akira Inoue , Masahiko Hata
发明人： Akira Inoue , Masahiko Hata
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/7371 , H01L29/1004
摘要： In an epitaxial substrate comprising a bipolar transistor structure having a collector layer (3), base layer (4) and emitter layer (5) on a GaAs substrate (2), the base layer (4) is configured a lower base layer (41) having a required carrier concentration, an upper base layer (42), and a low carrier concentration layer (43) provided between the lower base layer (41) and the upper base layer (42) that has a ballast effect. The lower base layer (41) or the upper base layer (42) may be omitted. The higher the temperature of the low carrier concentration layer (43) portion is, the easier it is for electrons to pass therethrough, which has the effect of raising the amplification factor, thereby helping the transistor heat stability characteristics.
摘要翻译：在包括在GaAs衬底（2）上具有集电极层（3），基底层（4）和发射极层（5））的双极晶体管结构的外延衬底中，基底层（4）被构造为下部基底层）具有设置在具有镇流效应的下基底层（41）和上基底层（42）之间的上基底层（42）和低载流子浓度层（43）。可以省略下基层（41）或上基层（42）。低载流子浓度层（43）部分的温度越高，电子越容易通过，这具有提高放大系数的作用，从而有助于晶体管的热稳定性。

49. 发明授权

US5441913A Process of making a semiconductor epitaxial substrate 失效
标题翻译：制造半导体外延基板的工艺
公开(公告)号：US5441913A
公开(公告)日：1995-08-15
申请号：US266680
申请日：1994-06-28
申请人： Masahiko Hata , Noboru Fukuhara , Hiroaki Takata , Katsumi Inui
发明人： Masahiko Hata , Noboru Fukuhara , Hiroaki Takata , Katsumi Inui
IPC分类号： H01L21/203 , H01L21/205 , H01L21/20
CPC分类号： H01L21/02395 , H01L21/02433 , H01L21/02463 , H01L21/02546 , H01L21/02576 , H01L21/0262 , H01L21/02631
摘要： A semiconductor epitaxial substrate and a process for producing the same, the semiconductor epitaxial substrate comprising a GaAs single-crystal substrate having thereon an In.sub.y Ga.sub.(1-y) As (0
摘要翻译：一种半导体外延基板及其制造方法，所述半导体外延基板包括其上具有In y Ga（1-y）As（0

50. 发明授权

US4976216A Apparatus for vapor-phase growth 失效
标题翻译：气相生长装置
公开(公告)号：US4976216A
公开(公告)日：1990-12-11
申请号：US269348
申请日：1988-11-10
申请人： Takayoshi Maeda , Masahiko Hata , Yasunari Zempo , Noboru Fukuhara , Hiroaki Takata
发明人： Takayoshi Maeda , Masahiko Hata , Yasunari Zempo , Noboru Fukuhara , Hiroaki Takata
IPC分类号： H01L21/205 , C23C16/458 , C30B25/02 , C30B25/08 , C30B25/12 , C30B25/14
CPC分类号： C30B25/14 , C23C16/4588 , C30B25/02 , C30B25/08 , C30B25/12 , C30B29/42
摘要： In an apparatus for vapor-phase growth which comprises a reactor having an inlet for the introduction of the gas containing a source material on its top and a susceptor provided in the downstream portion of the reactor, the improvement wherein the susceptor is generally in a conical or polygonal pyramid form consisting of an upper rectifying portion and a lower substrate holding portion, with the diameter of the susceptor in its lower portion increasing by a greater degree than in its upper portion.
摘要翻译：在用于气相生长的装置中，其包括具有用于引入其顶部具有源材料的气体的入口和设置在反应器的下游部分中的基座的反应器，其中基座大体上为圆锥形或由上部整流部分和下部基板保持部分组成的多边形棱锥形状，其下部中的基座的直径比其上部增加更大的程度。

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