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41. 发明申请

US20130202008A1 MONITORING CIRCUIT AND METHOD 有权
标题翻译：监测电路和方法
公开(公告)号：US20130202008A1
公开(公告)日：2013-08-08
申请号：US13368383
申请日：2012-02-08
申请人： James Edward MYERS , David Walter Flynn , Bal S. Sandhu
发明人： James Edward MYERS , David Walter Flynn , Bal S. Sandhu
IPC分类号： G01K13/00 , G01K15/00
CPC分类号： G01K7/346
摘要： A monitoring circuit for an integrated circuit comprises a non-temperature-inverted circuit and a temperature-inverted circuit. Operating parameters of the two circuits are measured, representing the propagation speed of signals in the respective circuits. In response to a change in temperature, the non-temperature-inverted circuit slows down and the temperature-inverted circuit speeds up. In contrast, in response to a change in operating voltage both circuits either speed up or slow down. This divergence in response to temperature and similar response to voltage enables the monitoring circuit to distinguish between changes in operating voltage and changes in operating temperature.
摘要翻译：集成电路的监视电路包括非温度反相电路和温度反相电路。测量两个电路的工作参数，表示各个电路中信号的传播速度。响应于温度变化，非温度反相电路减慢，温度反转电路加速。相比之下，响应于工作电压的变化，两个电路都加速或减慢。响应于温度的这种分歧和对电压的类似响应使得监测电路能够区分工作电压的变化和工作温度的变化。

42. 发明授权

US6034545A Macrocell for data processing circuit 失效
标题翻译：宏单元用于数据处理电路
公开(公告)号：US6034545A
公开(公告)日：2000-03-07
申请号：US15927
申请日：1998-01-30
申请人： David Walter Flynn
发明人： David Walter Flynn
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1733
摘要： The present invention provides a macrocell for a data processing circuit, comprising macrocell logic, and an interface for connecting the macrocell logic to a bus of the data processing circuit. The interface comprises: an input bus connected to an input bus terminal, an output bus connected to an output bus terminal, and a buffering circuit for buffering the output bus from the macrocell logic. Further, the interface has a mode input terminal for receiving a mode value, the mode value being arranged to control the buffering circuit. The buffering circuit is responsive to a first mode value to enter an inactive state when no data is being output from the macrocell, and is responsive to a second mode value to permanently drive the output bus. Hence, to enable the macrocell to be coupled to a unidirectional bus on the data processing circuit, the second mode value is supplied to the mode input terminal, whilst to enable the macrocell to be coupled to a bidirectional bus on the data processing circuit, the input bus terminal and output bus terminal are connected together externally to the macrocell, and the first mode value is supplied to the mode input terminal.
摘要翻译：本发明提供了一种用于数据处理电路的宏单元，包括宏单元逻辑，以及用于将宏单元逻辑连接到数据处理电路的总线的接口。该接口包括：连接到输入总线端子的输入总线，连接到输出总线端子的输出总线，以及用于从宏单元逻辑缓冲输出总线的缓冲电路。此外，接口具有用于接收模式值的模式输入端子，模式值被布置为控制缓冲电路。当没有数据从宏小区输出时，缓冲电路响应于第一模式值进入非活动状态，并且响应于第二模式值来永久驱动输出总线。因此，为了使宏单元能够耦合到数据处理电路上的单向总线，将第二模式值提供给模式输入端，同时使宏单元能够耦合到数据处理电路上的双向总线，输入总线端子和输出总线端子从外部连接到宏单元，第一模式值提供给模式输入端。

43. 发明授权

US5764173A Digital to analogue converter having input control bits for selecting a pulse width modulated output signal 失效
标题翻译：具有用于选择脉宽调制输出信号的输入控制位的数模转换器
公开(公告)号：US5764173A
公开(公告)日：1998-06-09
申请号：US715495
申请日：1996-09-18
申请人： David Walter Flynn
发明人： David Walter Flynn
IPC分类号： H03M1/10 , H03M1/06 , H03M1/66 , H03M1/68 , H03M1/82
CPC分类号： H03M1/664 , H03M1/68 , H03M1/822
摘要： A digital to analogue converter having a plurality of output stages 46. Each output stage 46 includes a tri-state buffer 54 that outputs an on-signal, an off-signal or a pulse width modulated signal PWM that is selected by a multiplexer 52 that operates under control of a chord decoder 50 that is responsive to exponent bits within the input digital signal value. If a pulse width modulated signal is selected, then its duty cycle is controlled by a pulse width modulated decoder 48 that is responsive to mantissa bits within the input digital signal value. A further output provides a pulse width modulated signal of a predetermined duty cycle that may be used as a reference signal to compensate for variations in the operation of the rest of the digital to analogue circuit.
摘要翻译：具有多个输出级46的数模转换器。每个输出级46包括三态缓冲器54，其输出由多路复用器52选择的接通信号，截止信号或脉宽调制信号PWM，在和解解码器50的控制下操作，该解码器响应输入数字信号值内的指数位。如果选择了脉宽调制信号，则其占空比由脉冲宽度调制解码器48控制，脉冲宽度调制解码器48响应输入数字信号值内的尾数位。另外的输出提供预定占空比的脉冲宽度调制信号，该脉冲宽度调制信号可用作参考信号，以补偿其余数字模拟电路的变化。

44. 发明授权

US08456223B2 Integrated circuit with power gating 有权
标题翻译：集成电路与电源门控
公开(公告)号：US08456223B2
公开(公告)日：2013-06-04
申请号：US13067776
申请日：2011-06-24
申请人： James Edward Myers , David Walter Flynn
发明人： James Edward Myers , David Walter Flynn
IPC分类号： H03K3/01
CPC分类号： H03K19/0016
摘要： An integrated circuit includes a main power rail, a ground power rail as well as a virtual main power rail and a virtual ground power rail. Combinatorial logic circuitry is connected to draw its power from the virtual main power rail and the virtual ground power rail. Signal value storage circuitry is connected to draw its power from one of the main power rail and the ground power rail with the other power connection being to a virtual rail. The integrated circuit has an operational mode, a retention mode and a power off mode. In the retention mode, the voltage difference across the combinatorial logic circuitry is a low power voltage difference insufficient to support data processing operations whereas the voltage difference across the signal value storage circuitry is higher and is sufficient to support signal value retention within the signal value storage circuitry.
摘要翻译：集成电路包括主电源轨，接地电源轨以及虚拟主电源轨和虚拟接地电源轨。组合逻辑电路连接起来，从虚拟主电源轨和虚拟接地电源轨中抽取电力。信号值存储电路被连接以从主电力轨和地电源轨之一拉动其电力，而另一个电力连接是虚拟轨道。集成电路具有操作模式，保持模式和关机模式。在保持模式下，组合逻辑电路之间的电压差是不足以支持数据处理操作的低功率电压差，而信号值存储电路两端的电压差较高，足以支持信号值存储器内的信号值保持电路。

45. 发明授权

US08451039B2 Apparatus for storing a data value in a retention mode 有权
标题翻译：用于将数据值存储在保持模式中的装置
公开(公告)号：US08451039B2
公开(公告)日：2013-05-28
申请号：US13067183
申请日：2011-05-13
申请人： James Edward Myers , John Philip Biggs , David Walter Flynn , Carsten Tradowsky
发明人： James Edward Myers , John Philip Biggs , David Walter Flynn , Carsten Tradowsky
IPC分类号： H03K3/289
CPC分类号： G11C14/0054
摘要： Apparatus for storing a data value in the form of a master-slave latch supporting zig-zag power gating is described. A NAND gate 52 at the output of the latch forces a predetermined retention signal value at the output from the latch during a retention mode. A scan multiplexer 42 at the input to the latch selects the scan input, which is the predetermined retention signal from another latch, during the retention mode. Within the latch power gated circuitry 32 is subject to zig-zag power gating using virtual power rails VDDZ and VSSZ so as to reduce the leakage current. State storing circuitry 34 is permanently connected to the power supplies VDDG, VSSG such that it is able to maintain whatever signal value is stored therein during the retention mode.
摘要翻译：描述了以支持Z形电源门控的主从锁存器的形式存储数据值的装置。在锁存器的输出处的NAND门52在保持模式期间迫使来自锁存器的输出处的预定保持信号值。在锁存器的输入处的扫描多路复用器42在保持模式期间选择作为来自另一锁存器的预定保持信号的扫描输入。在闩锁电源门控电路32内，使用虚拟电源线VDDZ和VSSZ进行Z形电源门控，以减少漏电流。状态存储电路34永久地连接到电源VDDG，VSSG，使得能够在保持模式期间保持其中存储的任何信号值。

46. 发明申请

US20120303985A1 State retention circuit adapted to allow its state integrity to be verified 有权
标题翻译：状态保持电路适于允许其状态完整性被验证
公开(公告)号：US20120303985A1
公开(公告)日：2012-11-29
申请号：US13067395
申请日：2011-05-27
申请人： David Walter Flynn
发明人： David Walter Flynn
IPC分类号： G06F1/32 , G06F12/00
CPC分类号： G01R31/318541 , G06F1/3237 , G06F1/3296 , G06F11/10 , G06F11/2236
摘要： A state retention component is provided which is configured to form part of data processing circuitry. The state retention component is configured to hold a state value at a node of the data processing circuitry when the data processing circuitry enters a low power mode. The state retention component comprises a scan input, wherein the state retention component configured, when a scan enable signal is asserted, to read in the state value from a scan input value applied at the scan input, and a scan output, wherein the state retention component is configured, when the scan enable signal is asserted, to read out the state value to the scan output. When the scan enable signal is not asserted, the state retention circuit outputs at the scan output a parity value, wherein the parity value is generated by combinatorial function circuitry on the basis of the state value and the scan input value, wherein the combinatorial function circuitry is configured such that the parity value inverts if either the state value or the scan input value changes, thus providing an external indication of the integrity of the state value held by the state retention component.
摘要翻译：提供状态保持组件，其被配置为形成数据处理电路的一部分。状态保持组件被配置为当数据处理电路进入低功率模式时，在数据处理电路的节点处保持状态值。状态保持部件包括扫描输入，其中状态保持部件被配置为当扫描使能信号被断言时，从在扫描输入处施加的扫描输入值读取状态值和扫描输出，其中状态保持当扫描启用信号被置位时，组件被配置为将扫描输出的状态值读出。当扫描使能信号未被置位时，状态保持电路在扫描输出端输出奇偶校验值，其中奇偶校验值由组合函数电路基于状态值和扫描输入值产生，其中组合函数电路被配置为使得如果状态值或扫描输入值改变，则奇偶校验值反转，从而提供由状态保持组件保持的状态值的完整性的外部指示。

47. 发明授权

US07181633B2 Data processing performance control based on a status signal indicating the maximum voltage that can be supported 有权
标题翻译：基于指示可支持的最大电压的状态信号的数据处理性能控制
公开(公告)号：US07181633B2
公开(公告)日：2007-02-20
申请号：US10715410
申请日：2003-11-19
申请人： David Walter Flynn
发明人： David Walter Flynn
IPC分类号： G06F1/26
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/124 , Y02D10/126 , Y02D10/128 , Y02D10/172
摘要： A data processing system includes a processor 46 operable to generate control signals to control one or more further circuits 4, 6 to adopt operational states to support different performance levels of the processor. The one or more further circuits generate current operation signals indicative of their current operation. Examples of further circuits are a clock generator 4 which generates a current operation signal indicative of a currently generated clock signal or possibly currently available clock signals. A voltage controller 6 may be a further circuit which serves to provide a power signal to the system and which generates a current operation signal indicative of the current maximum voltage level which the voltage controller is able to supply.
摘要翻译：数据处理系统包括处理器46，处理器46可操作以产生控制信号以控制一个或多个另外的电路4,6以采用操作状态来支持处理器的不同性能级别。一个或多个另外的电路产生指示其当前操作的电流操作信号。另外的电路的例子是时钟发生器4，其产生指示当前产生的时钟信号或可能当前可用的时钟信号的当前操作信号。电压控制器6可以是用于向系统提供功率信号并且产生指示电压控制器能够供应的当前最大电压电平的电流操作信号的另外的电路。

48. 发明授权

US06883102B2 Apparatus and method for performing power management functions 有权
标题翻译：用于执行电源管理功能的装置和方法
公开(公告)号：US06883102B2
公开(公告)日：2005-04-19
申请号：US10020511
申请日：2001-12-18
申请人： Gerard Richard Williams, III , Kim Rasmussen , David Walter Flynn
发明人： Gerard Richard Williams, III , Kim Rasmussen , David Walter Flynn
IPC分类号： G06F1/26 , G06F1/32 , G06F1/30 , G06F9/44 , G06F9/455
CPC分类号： G06F1/26 , G06F1/32
摘要： The present invention provides a data processing apparatus and method for testing power management instructions. The data processing apparatus comprises a processor for executing data processing instructions including power management instructions, at least one of the power management instructions being a command power management instruction. A power management controller is also provided for receiving command data from the processor when a command power management instruction is executed by the processor, and to control power management logic to perform an associated set of power management functions dependent on the command data. The data processing apparatus includes first power management logic controllable by the power management controller, with the power management controller also having an interface to enable communication with additional power management logic. In accordance with the present invention, the processor is arranged when executing the command power management instruction to specify within the command data provided to the power management controller whether an emulation mode of operation is set. The power management controller is arranged when the emulation mode is not set to initiate the associated set of power management functions dependent on the command data, whilst if the emulation mode is set it is arranged to only initiate a subset of the associated set of power management functions not requiring communication over the interface. By this approach, it is possible to perform some testing of power management software before all aspects of the power management hardware have been designed.
摘要翻译：本发明提供了一种用于测试电源管理指令的数据处理装置和方法。该数据处理装置包括一个处理器，用于执行包括功率管理指令的数据处理指令，该功率管理指令中的至少一个是指令功率管理指令。还提供电源管理控制器，用于当处理器执行命令电源管理指令时，从处理器接收命令数据，并且控制电源管理逻辑以根据命令数据执行一组相关的电源管理功能。数据处理装置包括由电源管理控制器控制的第一电源管理逻辑，电源管理控制器还具有能够与额外的电源管理逻辑通信的接口。根据本发明，处理器在执行指令功率管理指令时被配置，以在提供给功率管理控制器的命令数据内指定是否设置仿真操作模式。当仿真模式未被设置为根据命令数据启动相关联的一组功率管理功能时，布置功率管理控制器，而如果设置仿真模式，则其被设置为仅启动相关联的功率管理集合的子集功能不需要通过接口通信。通过这种方法，可以在设计电源管理硬件的所有方面之前对电源管理软件进行一些测试。

49. 发明授权

US6069611A Display palette programming utilizing frames of data which also contain color palette updating data to prevent display distortion or sparkle 失效
标题翻译：使用还包含调色板更新数据的数据帧来显示调色板编程，以防止显示失真或闪烁
公开(公告)号：US6069611A
公开(公告)日：2000-05-30
申请号：US828938
申请日：1997-03-28
申请人： David Walter Flynn , Ashley Miles Stevens , Lance Gregory Howarth
发明人： David Walter Flynn , Ashley Miles Stevens , Lance Gregory Howarth
IPC分类号： G09G5/06 , G09G5/02 , G09G5/04
CPC分类号： G09G5/06
摘要： A display palette system comprising a digital palette 16 supplied with frames of data 26. Each frame of data 26 includes a complete set of palette mapping data and control data 28 with which the digital palette 16 is programmed under control of a palette control circuit 24. The rows of logical pixel data that follow in the frame each terminate with row palette data RP that can be directed to reprogram the digital palette 16 part of the way through the display of a single frame.
摘要翻译：显示调色板系统，包括提供有数据帧26的数字调色板16.每帧数据26包括完整的调色板映射数据集和控制数据28，数字调色板16在调色板控制电路24的控制下被编程。帧中跟随的逻辑像素数据行各自以行调色板数据RP终止，该调色板数据可以通过单个帧的显示指向重新编程数字调色板16的一部分。

50. 发明授权

US5774083A Digital to analogue converter comprising a converting circuit and a reference circuit both being formed in a single integrated circuit 失效
标题翻译：数模转换器包括转换电路和参考电路，两者均形成在单个集成电路中
公开(公告)号：US5774083A
公开(公告)日：1998-06-30
申请号：US715595
申请日：1996-09-18
申请人： David Walter Flynn
发明人： David Walter Flynn
IPC分类号： H03M1/10 , H03M1/06 , H03M1/66 , H03M1/68 , H03M1/82 , H03M1/78
CPC分类号： H03M1/664 , H03M1/68 , H03M1/822
摘要： A digital to analogue converter having a plurality of output stages 46. Each output stage 46 includes a tri-state buffer 54 that outputs an on-signal, an off-signal or a pulse width modulated signal PWM that is selected by a multiplexer 52 that operates under control of a chord decoder 50 that is responsive to exponent bits within the input digital signal value. If a pulse width modulated signal is selected, then its duty cycle is controlled by a pulse width modulated decoder 48 that is responsive to mantissa bits within the input digital signal value. A further output provides a pulse width modulated signal of a predetermined duty cycle that may be used as a reference signal to compensate for variations in the operation of the rest of the digital to analogue circuit.
摘要翻译：具有多个输出级46的数模转换器。每个输出级46包括三态缓冲器54，其输出由多路复用器52选择的接通信号，截止信号或脉宽调制信号PWM，在和解解码器50的控制下操作，该解码器响应输入数字信号值内的指数位。如果选择了脉宽调制信号，则其占空比由脉冲宽度调制解码器48控制，脉冲宽度调制解码器48响应输入数字信号值内的尾数位。另外的输出提供预定占空比的脉冲宽度调制信号，该脉冲宽度调制信号可用作参考信号，以补偿其余数字模拟电路的变化。

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