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41. 发明申请

US20150296018A1 SYSTEM FOR THE MANAGEMENT OF OUT-OF-ORDER TRAFFIC IN AN INTERCONNECT NETWORK AND CORRESPONDING METHOD AND INTEGRATED CIRCUIT 审中-公开
标题翻译：互连网络中的无序交通管理系统和相应的方法与集成电路
公开(公告)号：US20150296018A1
公开(公告)日：2015-10-15
申请号：US14659159
申请日：2015-03-16
申请人： STMicroelectronics S.r.l.
发明人： Mirko Dondini , Daniele Mangano
IPC分类号： H04L29/08 , H04L12/721
CPC分类号： H04L67/1097 , G06F13/1626 , G06F13/4022 , G06F2213/0038 , H04L45/72
摘要： A system to manage out-of-order traffic in an interconnect network has initiators that provide requests through the interconnect network to memory resource targets and provide responses back through the interconnect network. The system includes components upstream the interconnect network to perform response re-ordering, which include memory to store responses from the interconnect network and a memory map controller to store the responses on a set of logical circular buffers. Each logical circular buffer corresponds to an initiator. The memory map controller computes an offset address for each buffer and stores an offset address of a given request received on a request path. The controller computes an absolute write memory address where responses are written in the memory, the response corresponding to the given request based on the given request offset address. The memory map controller also performs an order-controlled parallel read of the logical circular buffers and routes the data read from the memory to the corresponding initiator.
摘要翻译：用于管理互连网络中的乱序流量的系统具有通过互连网络向存储器资源目标提供请求并且通过互连网络提供响应的启动器。该系统包括互连网络上游的组件以执行响应重新排序，其包括用于存储来自互连网络的响应的存储器和存储映射控制器以将响应存储在一组逻辑循环缓冲器上。每个逻辑循环缓冲区对应于启动器。存储器映射控制器计算每个缓冲器的偏移地址，并存储在请求路径上接收的给定请求的偏移地址。控制器计算绝对写存储器地址，其中响应被写入存储器中，该响应对应于给定的请求，基于给定的请求偏移地址。存储器映射控制器还执行逻辑循环缓冲器的顺序控制的并行读取，并将从存储器读取的数据路由到相应的启动器。

42. 发明申请

US20130297913A1 METHOD AND DEVICE FOR ABORTING TRANSACTIONS, RELATED SYSTEM AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：用于交易的方法和设备，相关系统和计算机程序产品
公开(公告)号：US20130297913A1
公开(公告)日：2013-11-07
申请号：US13888062
申请日：2013-05-06
申请人： STMICROELECTRONICS S.R.L.
发明人： Daniele Mangano
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/3861 , G06F9/466 , G06F9/485 , G06F11/0766 , G06F11/0793 , G06F13/1605
摘要： Current tasks being executed in a set of modules of a signal processing system managed via an interface block are aborted so as to permit the execution of new tasks by pipelining eliminating transactions of said current tasks and executing transactions of the new tasks. Upon arrival of a signal to abort the current tasks, data and/or memory accesses present in said interface block are discarded.
摘要翻译：在通过接口块管理的信号处理系统的一组模块中执行的当前任务被中止，以允许通过流水线去除所述当前任务的事务和执行新任务的交易来执行新任务。当信号到达以中止当前任务时，丢弃存在于所述接口块中的数据和/或存储器访问。

43. 发明授权

US10788870B2 Reset circuit, corresponding device and method 有权
公开(公告)号：US10788870B2
公开(公告)日：2020-09-29
申请号：US16405086
申请日：2019-05-07
申请人： STMicroelectronics S.r.l.
发明人： Daniele Mangano , Gaetano Di Stefano , Mirko Dondini
IPC分类号： G06F1/24 , G06F11/267 , H03K3/037
摘要： A circuit includes a first node configured to receive a reset signal. A reset drive stage drives a reset node. The reset drive stage is coupled to the first node via a reset signal path to propagate the reset signal to the reset drive stage. The reset drive stage is activated as a result of assertion of a reset actuation state of the reset signal. A sensing node is coupled to the reset node via a signal sensing path. The sensing node is sensitive to a signal level of the reset node reaching a reset threshold. A reset signal hold circuit block is coupled to the first node and is configured to receive a reset command signal and assert the reset actuation state of the reset signal at the first node as a result of the reset command signal received.

44. 发明授权

US10451703B2 Method of interfacing a LC sensor and related system 有权
公开(公告)号：US10451703B2
公开(公告)日：2019-10-22
申请号：US16213534
申请日：2018-12-07
申请人： STMicroelectronics S.r.l.
发明人： Riccardo Condorelli , Daniele Mangano
IPC分类号： G01R35/00 , G01R27/26 , G01R27/02 , G01D3/028 , G01D5/24 , H02J7/04 , H02J7/34
摘要： A method of interfacing a LC sensor with a control unit is provided. The control unit may include first and second contacts, where the LC sensor is connected between the first and the second contact. A capacitor is connected between the first contact and a ground. To start the oscillation of the LC sensor, the method may include during a first phase, connecting the first contact to a supply voltage and placing the second contact in a high impedance state such that the capacitor is charged through the supply voltage. During a second phase, the first contact may be placed in a high impedance state, and the second contact connected to the ground such that the capacitor transfers charge towards the LC sensor. During a third phase, the first contact and the second contact may be placed in a high impedance state so the LC sensor is able to oscillate.

45. 发明授权

US10162038B2 Method of interfacing a LC sensor and related system 有权
公开(公告)号：US10162038B2
公开(公告)日：2018-12-25
申请号：US14739195
申请日：2015-06-15
申请人： STMICROELECTRONICS S.r.l.
发明人： Riccardo Condorelli , Daniele Mangano
IPC分类号： G01R35/00 , G01R27/26 , G01D5/24 , H02J7/04 , G01D3/028 , H02J7/34 , G01R27/02
摘要： A method of interfacing a LC sensor with a control unit is provided. The control unit may include first and second contacts, where the LC sensor is connected between the first and the second contact. A capacitor is connected between the first contact and a ground. To start the oscillation of the LC sensor, the method may include during a first phase, connecting the first contact to a supply voltage and placing the second contact in a high impedance state such that the capacitor is charged through the supply voltage. During a second phase, the first contact may be placed in a high impedance state, and the second contact connected to the ground such that the capacitor transfers charge towards the LC sensor. During a third phase, the first contact and the second contact may be placed in a high impedance state so the LC sensor is able to oscillate.

46. 发明授权

US10120006B2 Method of operating LC sensors, corresponding system and apparatus 有权
公开(公告)号：US10120006B2
公开(公告)日：2018-11-06
申请号：US15070509
申请日：2016-03-15
申请人： STMICROELECTRONICS S.R.L.
发明人： Riccardo Condorelli , Daniele Mangano
IPC分类号： G01R27/26 , G01D5/20 , H03K17/95
摘要： In one embodiment, an inductive/LC sensor device includes: an energy storage device for accumulating excitation energy, an LC sensor configured to oscillate using energy accumulated in the energy storage device and transferred to the LC sensor, an energy detector for detecting the energy accumulated in the energy storage device reaching a charge threshold, and at least one switch coupled with the energy detector for terminating accumulating excitation energy in the energy storage device when the charge threshold is detected having been reached by the energy detector.

47. 发明申请

US20170068594A1 METHOD OF MANAGING MEMORIES, CORRESPONDING DEVICE AND APPARATUS 有权
标题翻译：管理记忆的方法，相应的设备和设备
公开(公告)号：US20170068594A1
公开(公告)日：2017-03-09
申请号：US15080307
申请日：2016-03-24
申请人： STMicroelectronics Design and Application s.r.o. , STMicroelectronics S.R.L.
发明人： Daniele Mangano , Michele Alessandro Carrano , Gaetano Distefano , Antonin Fried
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G06F11/1068 , G06F11/1044 , G11C29/52
摘要： A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.
摘要翻译：一种方法包括：将第一数据存储在第一存储器模块的第一分区中，并将第二数据写入第二存储器模块的第一分区中，并且以第一操作模式和第二操作模式选择性地操作第一和第二存储器模块。第一操作模式包括在第二存储器模块的第二分区中写入用于第一数据的奇偶校验位和在第一存储器模块的第二分区中写入用于第二数据的奇偶校验位。第二操作模式包括在第一存储器模块和第二存储器模块中的一个或两个的第二分区中写入另外的数据而不是奇偶校验位。

48. 发明申请

US20140344485A1 COMMUNICATION SYSTEM FOR INTERFACING A PLURALITY OF TRANSMISSION CIRCUITS WITH AN INTERCONNECTION NETWORK, AND CORRESPONDING INTEGRATED CIRCUIT 有权
标题翻译：用于将多个传输电路与互连网络相互连接的通信系统和相应的集成电路
公开(公告)号：US20140344485A1
公开(公告)日：2014-11-20
申请号：US14278403
申请日：2014-05-15
申请人： STMicroelectronics S.r.l.
发明人： Mirko Dondini , Daniele Mangano , Giuseppe Falconeri
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A communication system is arranged to interface a plurality of transmission circuits with an interconnection network. Each transmission circuit generates read requests and/or write requests. The communication system includes a first circuit that operates independently of the communication protocol of the interconnection network. In particular, the first circuit includes, a) for each transmission circuit a communication interface configured for receiving the read requests and/or write requests from the respective transmission circuit, b) a segmentation circuit configured for dividing, i.e., segmenting, the read requests and/or write requests received from the transmission circuits into transfer segments, and c) an interleaving circuit configured for generating, via an operation of interleaving of the transfer segments, a series of segments. The communication system also includes a second circuit configured for converting the transfer segments of the series of segments into data packets according to the protocol of the interconnection network and for transmitting the data packets to the interconnection network.
摘要翻译：通信系统被布置为将多个传输电路与互连网络接口。每个传输电路产生读请求和/或写请求。通信系统包括独立于互连网络的通信协议操作的第一电路。特别地，第一电路包括：a）对于每个传输电路，配置用于从各个传输电路接收读取请求和/或写入请求的通信接口，b）分配电路，被配置为将读取请求和/或将从所述传输电路接收的请求写入传输段，以及c）被配置为经由所述传送段的交织操作生成一系列段的交织电路。通信系统还包括第二电路，其被配置为根据互连网络的协议将一系列段的传输段转换成数据包，并将数据包发送到互连网络。

49. 发明申请

US20130259146A1 CIRCUIT FOR ASYNCHRONOUS COMMUNICATIONS, RELATED SYSTEM AND METHOD 有权
标题翻译：异步通信电路，相关系统及方法
公开(公告)号：US20130259146A1
公开(公告)日：2013-10-03
申请号：US13854419
申请日：2013-04-01
申请人： STMICROELECTRONICS S.R.L.
发明人： Daniele Mangano , Salvatore Pisasale , Carmelo Pistritto
IPC分类号： H03M13/00 , H03M13/51
CPC分类号： H03M13/6522 , G06F13/4286 , H03M13/51
摘要： A completion-detector circuit for detecting completion of the transfer of asynchronous data on a communication channel with signal lines organized according to a delay-insensitive encoding (e.g., dual-rail, m-of-n, Berger encoding) comprises: logic circuitry for detecting the data on the aforesaid signal lines configured for: i) producing a first signal indicating the fact that the asynchronous data on the signal lines are stable; ii) producing a second signal indicating the fact that the signal lines are de-asserted; and an asynchronous finite-state machine supplied with the first signal and the second signal for producing a signal of detection of completion of transfer of the asynchronous data, the detection signal having: a first value, when the first signal is asserted; and a second value, when the second signal is asserted; and being on hold when neither one nor the other of said first signal and said second signal is asserted.
摘要翻译：一种完成检测器电路，用于检测在根据延迟不敏感编码（例如，双轨，m-of-n，Berger编码）组织的信号线在通信信道上完成异步数据的传输，包括：用于检测上述信号线上的数据，其配置用于：i）产生指示信号线上的异步数据是稳定的事实的第一信号; ii）产生指示信号线被断言的事实的第二信号; 以及提供有第一信号和第二信号的异步有限状态机，用于产生检测异步数据传输完成的信号，检测信号具有：第一值，当第一信号被断言时; 以及第二值，当所述第二信号被断言时; 并且当所述第一信号和所述第二信号的一个或另一个被断言时，它们处于保持状态。

50. 发明授权

US11025289B2 Power management method, corresponding system and apparatus 有权
公开(公告)号：US11025289B2
公开(公告)日：2021-06-01
申请号：US16800793
申请日：2020-02-25
申请人： STMicroelectronics S.r.l.
发明人： Daniele Mangano , Pasquale Butta′
IPC分类号： H04B1/40 , H02M1/00
摘要： A method for power management in an electronic circuit that comprises a processing system and an RF embedded circuit includes: generating a first regulated voltage with a power regulation module of the RF embedded circuit; generating a second regulated voltage from the first regulated voltage with a first linear regulator of the processing system; and controlling the power regulation module of the RF embedded circuit to operate according to a plurality of operation modes. The operation modes include: a first sleep mode in which a switched-mode power supply of the RF embedded circuit is off and a second linear regulator of the RF embedded circuit is off; a second sleep mode in which a switched-mode power supply is off and the second linear regulator is on; and a third sleep mode in which the switched-mode power supply is on and the second linear regulator is off.

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