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41. 发明授权

US08222136B2 Method of forming contacts for a semiconductor device 有权
标题翻译：形成半导体器件的触点的方法
公开(公告)号：US08222136B2
公开(公告)日：2012-07-17
申请号：US12906868
申请日：2010-10-18
申请人： Yuan-Tien Tu , Tsai-Chun Li , Huan-Just Lin , Shih-Chang Chen
发明人： Yuan-Tien Tu , Tsai-Chun Li , Huan-Just Lin , Shih-Chang Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76816
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a layer over a substrate. The method includes forming a first opening in the layer that exposes a first region of the substrate. The method includes removing a first oxidation layer formed over the first region through a first sputtering process. The method includes filling the first opening with a conductive material. The method includes forming a second opening in the layer that exposes a second region of the substrate, the second region being different from the first region. The method includes removing a second oxidation layer formed over the second region through a second sputtering process. One of the first and second sputtering processes is more powerful than the other.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成层。所述方法包括在所述层中形成暴露所述衬底的第一区域的第一开口。该方法包括通过第一溅射工艺去除在第一区域上形成的第一氧化层。该方法包括用导电材料填充第一开口。所述方法包括在所述层中形成暴露所述衬底的第二区域的第二开口，所述第二区域不同于所述第一区域。该方法包括通过第二溅射工艺除去在第二区域上形成的第二氧化层。第一和第二溅射工艺之一比另一个更强大。

42. 发明申请

US20120092418A1 SINGLE-NOZZLE INKJET HEAD 审中-公开
标题翻译：单喷嘴喷头
公开(公告)号：US20120092418A1
公开(公告)日：2012-04-19
申请号：US13272438
申请日：2011-10-13
申请人： Shih-Chang Chen , Shih-Che Chiu , Tsung-Pat Chou
发明人： Shih-Chang Chen , Shih-Che Chiu , Tsung-Pat Chou
IPC分类号： B41J2/14
CPC分类号： B41J2/14201 , B41J2202/15 , B41J2202/19
摘要： A single-nozzle inkjet head includes a first chamber member and a second chamber member. The first chamber member has a first flow channel. The second chamber member is detachably connected with the first chamber member. The second chamber member includes a main body, a nozzle plate and an actuator. The main body has a second flow channel, wherein the second flow channel is in communication with the first flow channel for transporting a fluid. The nozzle plate is disposed on the main body, and has a nozzle. The actuator is disposed on the nozzle plate, and located around the nozzle.
摘要翻译：单喷嘴喷墨头包括第一室构件和第二室构件。第一室构件具有第一流动通道。第二室构件与第一室构件可拆卸地连接。第二室构件包括主体，喷嘴板和致动器。主体具有第二流动通道，其中第二流动通道与用于输送流体的第一流动通道连通。喷嘴板设置在主体上，并具有喷嘴。致动器设置在喷嘴板上并位于喷嘴周围。

43. 发明授权

US08115263B2 Laminated silicon gate electrode 有权
标题翻译：层压硅栅电极
公开(公告)号：US08115263B2
公开(公告)日：2012-02-14
申请号：US11041178
申请日：2005-01-24
申请人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
发明人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L29/78
CPC分类号： H01L21/02532 , H01L21/02595 , H01L21/2022 , H01L21/28035 , H01L21/3003 , H01L29/4925 , H01L29/78
摘要： Within a method for forming a silicon layer, there is employed at least one sub-layer formed of a higher crystalline silicon material and at least one sub-layer formed of a lower crystalline silicon material. The lower crystalline silicon material is formed employing a hydrogen treatment of the higher crystalline silicon material. The method is particularly useful for forming polysilicon based gate electrodes with enhanced dimensional control and enhanced performance.
摘要翻译：在形成硅层的方法中，使用由较高结晶硅材料形成的至少一个子层和由下部结晶硅材料形成的至少一个子层。使用较高结晶硅材料的氢处理形成下部结晶硅材料。该方法对于形成具有增强尺寸控制和增强性能的多晶硅基栅电极特别有用。

44. 发明申请

US20110318915A1 PROCESS TO MAKE HIGH-K TRANSISTOR DIELECTRICS 有权
标题翻译：制造高K晶体管电介质的工艺
公开(公告)号：US20110318915A1
公开(公告)日：2011-12-29
申请号：US13224059
申请日：2011-09-01
申请人： Liang-Gi Yao , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
发明人： Liang-Gi Yao , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/28 , B82Y40/00
CPC分类号： H01L21/0228 , C23C16/56 , H01L21/02145 , H01L21/02153 , H01L21/02159 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/3141 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/4966 , H01L29/517
摘要： A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.
摘要翻译：一种减少高k电介质层中的杂质的方法，包括以下步骤。提供基板。在衬底上形成具有杂质的高k电介质层。高k电介质层由MOCVD或ALCVD工艺形成。退火高k电介质层以减少高k电介质层内的杂质。

45. 发明申请

US20110048146A1 FEED DRIVE MECHANISM AND CONNECTING ASSEMBLY THEREOF 有权
标题翻译：进给驱动机构和连接组件
公开(公告)号：US20110048146A1
公开(公告)日：2011-03-03
申请号：US12629538
申请日：2009-12-02
申请人： Feng Ming Ou , Jen Ji Wang , Shih-Chang Chen , Chien Chih Chiu , Yi Huang Liou
发明人： Feng Ming Ou , Jen Ji Wang , Shih-Chang Chen , Chien Chih Chiu , Yi Huang Liou
IPC分类号： F16H29/20 , F16B7/00
CPC分类号： F16H25/24 , B23Q5/40 , F16H2025/2445 , Y10T74/18576 , Y10T74/18648 , Y10T403/3966
摘要： A feed drive mechanism and a connecting assembly thereof are described. The connecting assembly includes a main body and an outer sleeve. The main body has a connecting plate and an inner sleeve connected to a side surface of the connecting plate. Two opposite side surfaces of the connecting plate are respectively fixed on a screw nut seat and a lead screw nut of the feed drive mechanism, and a channel surrounds an outer side surface of the inner sleeve. The outer sleeve is sleeved on the outer side surface of the inner sleeve, enables the channel to be formed into a sealed space, and has an inlet and an outlet respectively communicating with the channel, thereby injecting a cooling medium into the channel.
摘要翻译：描述了馈送驱动机构及其连接组件。连接组件包括主体和外套筒。主体具有连接板和连接到连接板的侧表面的内套筒。连接板的两个相对的侧表面分别固定在进给驱动机构的螺母座和导螺杆螺母上，并且通道围绕内套筒的外侧表面。外套筒套在内套筒的外侧表面上，使得通道能够形成为密封空间，并且具有分别与通道连通的入口和出口，从而将冷却介质注入通道。

46. 发明申请

US20100107195A1 Program preference setting method and system for a broadcasting video program 审中-公开
标题翻译：播放视频节目的节目偏好设置方法和系统
公开(公告)号：US20100107195A1
公开(公告)日：2010-04-29
申请号：US12320223
申请日：2009-01-22
申请人： Ming-Jen Hsu , Shih-Chang Chen
发明人： Ming-Jen Hsu , Shih-Chang Chen
IPC分类号： H04N5/445 , G06F3/00
CPC分类号： H04N5/44543 , H04N21/47214 , H04N21/4828
摘要： A program preference setting method and system for broadcasting video program are disclosed. The preference setting method and system are generally applied to an Electronic Program Guide (EPG) for the digital television program. More particularly, a program preference setting system is provided to be embedded in the digital broadcast program receiving and playing device. One or more keywords may be set to the electronic program guide. Through comparison between the keyword(s) and the content of EPG, the positive comparison result is found for scheduling a program sequence. Further, a reminder corresponding to the program sequence may be set in a certain period through the system, and shown on the screen for user's convenience.
摘要翻译：公开了一种用于广播视频节目的节目偏好设置方法和系统。偏好设定方法和系统通常应用于数字电视节目的电子节目指南（EPG）。更具体地，提供了一种嵌入在数字广播节目接收和播放装置中的节目偏好设置系统。可以将一个或多个关键字设置到电子节目指南。通过比较关键词和EPG的内容，找到了对程序序列进行调度的正比较结果。此外，可以通过系统在一定时间段内设置与程序序列相对应的提醒，并且为了方便用户而在屏幕上显示。

47. 发明授权

US07638396B2 Methods for fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07638396B2
公开(公告)日：2009-12-29
申请号：US11725453
申请日：2007-03-20
申请人： Da-Yuan Lee , Chi-Chun Chen , Shih-Chang Chen
发明人： Da-Yuan Lee , Chi-Chun Chen , Shih-Chang Chen
IPC分类号： H01L21/8234
CPC分类号： H01L21/28202 , H01L21/823462 , H01L27/088 , H01L29/518 , H01L29/78
摘要： A method for fabricating a semiconductor device comprises providing a silicon-containing substrate with first, second, and third regions. First, second, and third gate stacks respectively overlie a portion of the silicon-containing substrate in the first, second, and third regions. A spacer is formed on opposing sidewalls of each of the first, second, and third gate stacks, the spacer overlying a portion of the silicon-containing substrate in the first, second, and third regions, respectively. A source/drain region is formed in a portion of the silicon-containing substrate in the first, second, and third regions, with the source/drain region adjacent to the first, second, and third gate stacks, respectively. The first, second, and third gate stacks have first, second, and third gate dielectric layers of various thicknesses and at least one thereof with a relatively thin thickness is treated by NH3-plasma, having a nitrogen-concentration of about 1013˜1021 atoms/cm2 therein.
摘要翻译：一种制造半导体器件的方法包括提供含有第一，第二和第三区域的含硅衬底。第一，第二和第三栅极堆叠分别覆盖在第一，第二和第三区域中的含硅衬底的一部分。间隔件形成在第一，第二和第三栅极堆叠中的每一个的相对侧壁上，间隔物分别在第一，第二和第三区域中的含硅衬底的一部分上方覆盖。源/漏区形成在第一，第二和第三区域中的含硅衬底的一部分中，源/漏区分别与第一，第二和第三栅堆叠相邻。第一，第二和第三栅极堆叠具有各种厚度的第一，第二和第三栅极电介质层，并且具有相对较薄厚度的至少一个具有相对薄的厚度的NH 3等离子体具有约1013〜1021原子的氮浓度 / cm2。

48. 发明申请

US20080199978A1 System and method for film stress and curvature gradient mapping for screening problematic wafers 有权
标题翻译：用于筛选有问题的晶片的膜应力和曲率梯度映射的系统和方法
公开(公告)号：US20080199978A1
公开(公告)日：2008-08-21
申请号：US11707662
申请日：2007-02-16
申请人： Hsueh-Hung Fu , Chih-Wei Chang , Shih-Chang Chen , Chin-Piao Chang , Shing-Chyang Pan , Wei-Jung Lin , Tsung-Hsun Huang
发明人： Hsueh-Hung Fu , Chih-Wei Chang , Shih-Chang Chen , Chin-Piao Chang , Shing-Chyang Pan , Wei-Jung Lin , Tsung-Hsun Huang
IPC分类号： G01R31/26
CPC分类号： G01R31/2831 , H01L22/12
摘要： A method of testing a wafer after a current top layer is formed over the wafer. Stress data is collected for the wafer after forming the current top layer. The stress data is derived from changes in wafer curvature. The stress data includes: stress-xx in an x direction and stress-yy in a y direction for each area of a set of finite areas on the wafer, the stress-xx and stress-yy both being derived from wafer-curvature-change-xx in the x direction for each area of the set of finite areas and from wafer-curvature-change-yy in the y direction for each area of the set of finite areas; and the stress-xy being derived from wafer-curvature-change-xy, wherein wafer-curvature-change-xy is a change in wafer twist in the x-y plane for each area of the set of finite areas. A stress gradient vector (and/or its norm) is calculated and used to evaluate the investigating single or multiple accumulated layer.
摘要翻译：在晶片上形成当前顶层之后测试晶片的方法。在形成当前顶层之后，为晶片收集应力数据。应力数据来源于晶片曲率的变化。应力数据包括：在x方向上的应力x x和在晶片上的一组有限区域的每个区域的ay方向上的应力yy，应力xx和应力yy都源自晶片曲率变化 - x x在x方向上对于有限区域集合中的每个区域以及从y方向的晶片曲率变化yy到该有限区域集合中的每个区域; 并且应力xy从晶片曲率变化xy得到，其中晶片曲率变化xy是在该有限区域的每个区域的x-y平面中的晶片扭转的变化。应力梯度矢量（和/或其范数）被计算并用于评估调查单个或多个累积层。

49. 发明授权

US07410854B2 Method of making FUSI gate and resulting structure 有权
标题翻译：制作FUSI门和结构的方法
公开(公告)号：US07410854B2
公开(公告)日：2008-08-12
申请号：US11543410
申请日：2006-10-05
申请人： Liang-Gi Yao , Hun-Jan Tao , Shih-Chang Chen , Mong-Song Liang
发明人： Liang-Gi Yao , Hun-Jan Tao , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823835 , H01L21/28097 , H01L29/4975 , H01L29/665 , H01L29/66545 , H01L29/6656
摘要： Generally disclosed is a method of a device comprising forming a polysilicon stack including a first and a second polysilicon layer with an intervening etch stop layer, wherein the first polysilicon layer height is at least one third a height of the polysilicon stack height, removing the second polysilicon layer and the etch stop layer, and reacting the first polysilicon layer with a metal to fully silicide the first polysilicon layer. Fully silicided (FUSI) gates can hence be formed with uniform gate height. The thin first polysilicon layer allows for siliciding with a lower thermal budge and with better uniformity of the silicide concentration throughout the layer.
摘要翻译：通常公开的是一种器件的方法，包括用中间蚀刻停止层形成包括第一和第二多晶硅层的多晶硅堆叠，其中第一多晶硅层高度为多晶硅叠层高度的至少三分之一高度，多晶硅层和蚀刻停止层，并使第一多晶硅层与金属反应以使第一多晶硅层完全硅化。因此，可以形成具有均匀栅极高度的全硅化（FUSI）栅极。薄的第一多晶硅层允许以更低的热辐射进行硅化，并且在整个层中具有更好的硅化物浓度的均匀性。

50. 发明申请

US20080160709A1 Advanced activation approach for MOS devices 有权
标题翻译： MOS器件的高级激活方法
公开(公告)号：US20080160709A1
公开(公告)日：2008-07-03
申请号：US11648371
申请日：2006-12-29
申请人： Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Keh-Chiang Ku , Chun-Feng Nieh , Li-Ting Wang , Hsun Chang
发明人： Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Keh-Chiang Ku , Chun-Feng Nieh , Li-Ting Wang , Hsun Chang
IPC分类号： H01L21/336
CPC分类号： H01L21/268 , H01L21/324 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a source/drain region adjacent the gate dielectric and the gate electrode; forming an absorption-capping layer over the source/drain region and the gate electrode; performing an activation by applying a high-energy light to the absorption-capping layer; and removing the absorption-capping layer.
摘要翻译：一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在栅极电介质上形成栅电极; 形成邻近所述栅极电介质和所述栅电极的源极/漏极区域; 在源极/漏极区域和栅极电极上形成吸收覆盖层; 通过向吸收覆盖层施加高能量光来进行激活; 并去除吸收层。

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