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41. 发明授权

US07005319B1 Global planarization of wafer scale package with precision die thickness control 有权
标题翻译：具有精密模具厚度控制的晶圆级封装的全局平面化
公开(公告)号：US07005319B1
公开(公告)日：2006-02-28
申请号：US10993941
申请日：2004-11-19
申请人： Howard Hao Chen , Louis L. Hsu , Brian L. Ji
发明人： Howard Hao Chen , Louis L. Hsu , Brian L. Ji
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L25/50 , H01L21/6835 , H01L23/13 , H01L23/5389 , H01L24/24 , H01L24/29 , H01L24/82 , H01L24/83 , H01L25/0655 , H01L25/16 , H01L2221/6835 , H01L2224/24227 , H01L2224/83192 , H01L2224/8385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01032 , H01L2924/01033 , H01L2924/01043 , H01L2924/07802 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/19041 , H01L2924/19042 , Y10S438/977
摘要： In accordance with the present invention, a method for producing at least two different chips with a controlled total chip thickness such that when these chips are placed into a corresponding pocket of a plurality of pockets located in a wafer chip carrier wherein each of the plurality of pockets have a total pocket depth (Tdp) at least substantially equal to one another, a substantially planarized top surface of said wafer chip carrier is achieved. The method comprises forming at least a first chip on a first dummy carrier and at least a second chip different from the first chip on a separate second dummy carrier using partial wafer bonding and partial wafer dicing. The method further includes using a chip thickness control mechanism in conjunction with said partial wafer bonding and partial wafer dicing in forming the at least a first chip and at least second chip different from the first chip, such that the at least first chip and the at least second different chip formed from each carrier each have a final total chip thickness (FTC) which is substantially equal to one another, and an FTC which is substantially equal to a total pocket depth (Tdp) of each of the uniform pockets of said wafer chip carrier, minus the final thickness of an attaching material (FTG) used within said each respective pocket.
摘要翻译：根据本发明，一种用于制造具有受控总芯片厚度的至少两个不同芯片的方法，使得当这些芯片被放置在位于晶片芯片载体中的多个凹穴的相应凹穴中时，其中多个口袋具有至少基本上彼此相等的总口袋深度（Tdp），实现了所述晶片芯片载体的基本平坦化的顶表面。该方法包括使用部分晶片接合和部分晶片切割，在第一虚设载体上形成至少第一芯片和至少第二芯片，该第一芯片与第一芯片不同于分开的第二虚设载体。该方法还包括在形成至少第一芯片和与第一芯片不同的至少第二芯片的同时，使用芯片厚度控制机构与所述部分晶片结合和部分晶片切割相结合，使得至少第一芯片和在从每个载体形成的最小的第二不同的芯片各自具有彼此基本相等的最终的总芯片厚度（FTC），以及基本上等于所述晶片的每个均匀袋的总袋深度（Tdp）的FTC 芯片载体减去在每个相应的口袋内使用的附着材料（FTG）的最终厚度。

42. 发明授权

US06980824B2 Method and system for optimizing transmission and reception power levels in a communication system 有权
标题翻译：用于优化通信系统中的发射和接收功率电平的方法和系统
公开(公告)号：US06980824B2
公开(公告)日：2005-12-27
申请号：US10249546
申请日：2003-04-17
申请人： Louis L. Hsu , Brian L. Ji , Karl D. Selander , Michael A. Sorna
发明人： Louis L. Hsu , Brian L. Ji , Karl D. Selander , Michael A. Sorna
IPC分类号： H04B7/005 , H04B7/00
CPC分类号： H04W52/20
摘要： A method and system are disclosed herein for determining optimum power level settings for a transmitter and receiver pair of a communication system having a plurality of transmitter and receiver pairs, as determined with respect to bit error rate. In the method disclosed herein, the power levels of a transmitter and a receiver pair coupled to communicate over a duplex communication link are set to initial values. The bit error rate is then determined over the link. Then, the power level of the transmitter, the receiver, or both, is altered, incrementally, and the effect upon the bit error rate is determined. When an improvement appears in the bit error rate at an altered power level, the power level of the transmitter, the receiver or both, are set to the altered power level at which the improvement is found. The steps of incrementally altering power levels, determining the bit error rate, and establishing new power level settings when there is an improvement are repeated until power levels are determined at which the bit error rate is optimized.
摘要翻译：本文公开了一种用于确定具有多个发射机和接收机对的通信系统的发射机和接收机对的最佳功率电平设置的方法和系统，如针对误码率确定的。在本文公开的方法中，耦合到通过双工通信链路进行通信的发射机和接收机对的功率电平被设置为初始值。然后通过链路确定误码率。然后，发送器，接收器或两者的功率电平被改变，递增地，并且确定对误码率的影响。当在改变的功率电平上出现比特错误率的改进时，发射机，接收机或两者的功率电平被设置为发现改进的改变的功率电平。重复改变功率级别，确定误码率和建立新的功率电平设置的步骤，直到确定位误码率被优化的功率电平为止。

43. 发明授权

US06975140B2 Adaptive data transmitter having rewriteable non-volatile storage 失效
标题翻译：自适应数据发射机具有可重写的非易失性存储
公开(公告)号：US06975140B2
公开(公告)日：2005-12-13
申请号：US10707199
申请日：2003-11-26
申请人： Louis L. Hsu , Brian L. Ji , William F. Washburn
发明人： Louis L. Hsu , Brian L. Ji , William F. Washburn
IPC分类号： H03H21/00 , H04L25/03 , H04L27/04 , H03H19/0175
CPC分类号： H04L25/03343 , H03H21/0012
摘要： A data transmitter and transmitting method are provided in which an adaptive finite impulse response (FIR) driver has a plurality of taps to which coefficients having updateable values are applied. The FIR driver has a transfer function between an input stream of data bits and an output stream of data bits such that each data bit output from the FIR driver has an amplitude adjusted as a function of the values of a plurality of data bits of the input stream, and the values of the coefficients. The data transmitter includes a rewriteable non-volatile storage, operable to be rewritten with control information representing the values of the coefficients updated during operation of the FIR driver.
摘要翻译：提供了一种数据发送器和发送方法，其中自适应有限脉冲响应（FIR）驱动器具有应用具有可更新值的系数的多个抽头。 FIR驱动器在数据位的输入流和数据位的输出流之间具有传递函数，使得从FIR驱动器输出的每个数据位的幅度根据输入的多个数据位的值而被调整流，以及系数的值。数据发送器包括可重写的非易失性存储器，可操作以用表示在FIR驱动器的操作期间更新的系数的值的控制信息进行重写。

44. 发明申请

US20120120701A1 TERNARY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES 审中-公开
标题翻译：使用相位变更设备的内容可寻址存储器
公开(公告)号：US20120120701A1
公开(公告)日：2012-05-17
申请号：US13350823
申请日：2012-01-16
申请人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
发明人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C13/0004
摘要： A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
摘要翻译：一种具有多个存储单元的内容可寻址存储器件，其存储高，低和不关心的三进制数据值。内容可寻址存储器件的一个方面是在存储器单元中使用第一存储器元件和第二存储器元件。第一和第二存储器元件以并联电路电耦合到匹配线。第一存储器元件耦合到第一字线，并且第二存储器元件耦合到第二字线。如果三进制数据值低，则第一存储器元件被配置为存储低电阻状态，并且如果三进制数据值高或不在乎，则高电阻状态。如果三进制数据值高，则第二存储器元件被配置为存储低电阻状态，并且如果三进制数据值为低或不关心，则存在高电阻状态。

45. 发明授权

US08054662B2 Content addressable memory array 有权
标题翻译：内容可寻址存储器阵列
公开(公告)号：US08054662B2
公开(公告)日：2011-11-08
申请号：US12549752
申请日：2009-08-28
申请人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
发明人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C7/1006 , G11C11/5678 , G11C13/0004
摘要： A memory device for storing one or more addresses includes a match line and first and second memory cells that form a 2-bit memory cell. Each memory cell includes two memory elements coupled to a match line and selection lines coupled thereto. The selection lines provide a signal representative of a logical combination of at least two different inputs.
摘要翻译：用于存储一个或多个地址的存储器件包括匹配线和形成2位存储器单元的第一和第二存储器单元。每个存储器单元包括耦合到匹配线的两个存储器元件和与其耦合的选择线。选择线提供表示至少两个不同输入的逻辑组合的信号。

46. 发明授权

US08030145B2 Back-gated fully depleted SOI transistor 有权
标题翻译：后栅极完全耗尽的SOI晶体管
公开(公告)号：US08030145B2
公开(公告)日：2011-10-04
申请号：US12684225
申请日：2010-01-08
申请人： Leland Chang , Brian L. Ji , Arvind Kumar , Amlan Majumdar , Katherine Saenger , Leathen Shi , Jeng-Bang Yau
发明人： Leland Chang , Brian L. Ji , Arvind Kumar , Amlan Majumdar , Katherine Saenger , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L21/84
CPC分类号： H01L21/2652 , G03F9/7084 , H01L21/26506 , H01L21/2654 , H01L21/26553 , H01L21/2658 , H01L21/6835 , H01L23/544 , H01L29/78648 , H01L2221/68318 , H01L2221/68363 , H01L2221/68377 , H01L2223/54426 , H01L2224/80006 , H01L2224/8013 , H01L2224/802 , H01L2924/01019 , H01L2924/12044 , H01L2924/13091
摘要： A fully depleted semiconductor-on-insulator (FDSOI) transistor structure includes a back gate electrode having a limited thickness and aligned to a front gate electrode. The back gate electrode is formed in a first substrate by ion implantation of dopants through a first oxide cap layer. Global alignment markers are formed in the first substrate to enable alignment of the front gate electrode to the back gate electrode. The global alignment markers enable preparation of a virtually flat substrate on the first substrate so that the first substrate can be bonded to a second substrate in a reliable manner.
摘要翻译：完全耗尽的绝缘体上半导体（FDSOI）晶体管结构包括具有有限厚度并与前栅电极对准的背栅电极。背栅极通过第一氧化物覆盖层通过离子注入掺杂剂形成在第一衬底中。在第一衬底中形成全局对准标记，以使前栅电极与背栅电极对准。全局校准标记使得能够在第一衬底上制备实质上平坦的衬底，使得第一衬底可以以可靠的方式结合到第二衬底。

47. 发明申请

US20110051486A1 CONTENT ADDRESSABLE MEMORY REFERENCE CLOCK 有权
标题翻译：内容可寻址内存参考时钟
公开(公告)号：US20110051486A1
公开(公告)日：2011-03-03
申请号：US12549772
申请日：2009-08-28
申请人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
发明人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
IPC分类号： G11C15/00 , G11C11/00 , G11C7/02
CPC分类号： G11C15/046 , G11C13/0004
摘要： A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled thereto, the reference memory cells being of the same type and the memory cells. The system also includes a match line sensor coupled to the reference match line and the match detector that determines a characteristic of the reference match line and provides a timing signal to the match detector based on the characteristic.
摘要翻译：存储器系统包括包括多个匹配线的内容可寻址存储器（CAM），每个匹配线具有耦合到其上的多个存储器单元。该系统还包括耦合到CAM的匹配检测器和具有耦合到其上的多个参考存储器单元的参考匹配线，参考存储器单元是相同类型的存储器单元。该系统还包括耦合到参考匹配线的匹配线传感器和匹配检测器，其确定参考匹配线的特性，并且基于该特性向匹配检测器提供定时信号。

48. 发明申请

US20110051482A1 CONTENT ADDRESSABLE MEMORY ARRAY PROGRAMMED TO PERFORM LOGIC OPERATIONS 有权
标题翻译：内容可寻址的存储阵列编程执行逻辑操作
公开(公告)号：US20110051482A1
公开(公告)日：2011-03-03
申请号：US12549740
申请日：2009-08-28
申请人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
发明人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
IPC分类号： G11C15/00 , G11C11/00 , G11C7/00
CPC分类号： G11C15/046 , G11C7/1006 , G11C13/0004
摘要： A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed.
摘要翻译：用于对两个或多个输入变量执行逻辑运算的存储器件包括匹配线和第一和第二存储器单元。第一和第二存储单元集体地包括第一，第二，第三和第四存储元件。第一，第二，第三和第四存储器元件可以具有在其中编程的第一值或第二值，并且其中基于特定逻辑功能将第一，第二，第三和第四存储器元件编程为高电阻值或低电阻值被执行。

49. 发明授权

US07751217B2 Content addressable memory using phase change devices 有权
标题翻译：内容可寻址内存使用相变设备
公开(公告)号：US07751217B2
公开(公告)日：2010-07-06
申请号：US12166311
申请日：2008-07-01
申请人： Chung H. Lam , Brian L. Ji , Robert K. Montoye , Bipin Rajendran
发明人： Chung H. Lam , Brian L. Ji , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00
CPC分类号： G11C13/0004 , G11C15/046
摘要： Content addressable memory device utilizing phase change devices. An aspect of the content addressable memory device is the use of a comparatively lower power search-line access element and a comparatively higher power word-line access element. The word-line access element is only utilized during write operations and the search-line access element is only utilized during search operations. The word-line access element being electrically coupled to a second end of a phase change memory element and a word-line. The search-line access element also being electrically coupled to the second end of the phase change memory element and a search-line. The search-line being electrically coupled to a match-line. A bit-line is electrically coupled to a first end of the phase change memory element. Additionally, a complementary set of access elements, a complementary phase change memory element, a complementary search-line, and a complementary bit-line are also included in the content addressable memory device.
摘要翻译：使用相变装置的内容寻址存储装置。内容可寻址存储器件的一个方面是使用相对较低功率的搜索线访问元件和相对较高功率的字线访问元件。字线访问元件仅在写入操作期间使用，并且搜索线访问元件仅在搜索操作期间被使用。字线访问元件电耦合到相变存储器元件的第二端和字线。搜索线访问元件还电耦合到相变存储元件的第二端和搜索线。搜索线电耦合到匹配线。位线电耦合到相变存储元件的第一端。此外，内容可寻址存储器件中还包括互补的一组存取元件，互补相变存储器元件，互补搜索线和互补位线。

50. 发明授权

US07660350B2 High-speed multi-mode receiver 失效
标题翻译：高速多模接收机
公开(公告)号：US07660350B2
公开(公告)日：2010-02-09
申请号：US12218272
申请日：2008-07-14
申请人： Louis C. Hsu , Brian L. Ji , James S. Mason , Karl D. Selander , Michael A. Soma , Steven J. Zier
发明人： Louis C. Hsu , Brian L. Ji , James S. Mason , Karl D. Selander , Michael A. Soma , Steven J. Zier
IPC分类号： H04B3/46
CPC分类号： H04L25/085 , H03F1/3241 , H04L25/0278 , H04L25/0292 , H04L25/03343 , H04L25/061 , H04L2025/0349 , H04L2025/03566 , H04L2025/03617 , H04L2025/03808
摘要： A data receiver is provided which is operable to receive a signal controllably pre-distorted and transmitted by a transmitter, to generate information for adjusting the pre-distortion applied to the signal transmitted by the transmitter, and to transmit the information to the transmitter. The receiver is further operable to perform adaptive equalization to receive the signal transmitted by the transmitter.
摘要翻译：提供了一种数据接收器，其可操作以接收由发射机可控地预失真和发送的信号，以产生用于调整应用于由发射机发送的信号的预失真的信息，并将该信息发送到发射机。接收机还可操作以执行自适应均衡以接收由发射机发送的信号。

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