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41. 发明授权

US07541267B1 Reversed T-shaped finfet 失效
标题翻译：反转T形finfet
公开(公告)号：US07541267B1
公开(公告)日：2009-06-02
申请号：US11765611
申请日：2007-06-20
申请人： Haihong Wang , Shibly S. Ahmed , Ming-Ren Lin , Bin Yu
发明人： Haihong Wang , Shibly S. Ahmed , Ming-Ren Lin , Bin Yu
IPC分类号： H01L21/28
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66795 , H01L29/7842
摘要： A method includes forming a first rectangular mesa from a layer of semiconducting material and forming a first dielectric layer around the first mesa. The method further includes forming a first rectangular mask over a first portion of the first mesa leaving an exposed second portion of the first mesa and etching the exposed second portion of the first mesa to produce a reversed T-shaped fin from the first mesa.
摘要翻译：一种方法包括从半导体材料层形成第一矩形台面并在第一台面周围形成第一介电层。该方法还包括在第一台面的第一部分上形成第一矩形掩模，离开第一台面的暴露的第二部分并蚀刻第一台面的暴露的第二部分以从第一台面产生反向的T形翅片。

42. 发明申请

US20070141791A1 DOPED STRUCTURE FOR FINFET DEVICES 有权
标题翻译： FINFET器件的DOPED结构
公开(公告)号：US20070141791A1
公开(公告)日：2007-06-21
申请号：US11677404
申请日：2007-02-21
申请人： Ming-Ren Lin , Bin Yu
发明人： Ming-Ren Lin , Bin Yu
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/4908 , H01L29/66795 , H01L29/78687
摘要： A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.
摘要翻译：半导体器件包括衬底和衬底上的绝缘层。半导体器件还包括形成在绝缘层上的翅片结构，其中鳍结构包括第一和第二侧表面，形成在鳍结构的第一和第二侧表面上的电介质层，形成在电介质层附近的第一栅电极在翅片结构的第一侧表面上形成与鳍结构的第二侧表面上的电介质层相邻的第二栅电极，以及在半导体器件的沟道区中形成在鳍结构的上表面上的掺杂结构。

43. 发明授权

US07078278B2 Dual-metal CMOS transistors with tunable gate electrode work function and method of making the same 有权
标题翻译：具有可调栅电极功能的双金属CMOS晶体管及其制作方法
公开(公告)号：US07078278B2
公开(公告)日：2006-07-18
申请号：US10833073
申请日：2004-04-28
申请人： James Pan , Ming-Ren Lin
发明人： James Pan , Ming-Ren Lin
IPC分类号： H01L28/80
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823842
摘要： A dual-metal CMOS arrangement and method of making the same provides a substrate and a plurality of NMOS devices and PMOS devices formed on the substrate. Each of the plurality of NMOS devices and PMOS devices have gate electrodes. Each NMOS gate electrode includes a first silicide region on the substrate and a first metal region on the first silicide region. The first silicide region of the NMOS gate electrode consists of a first silicide having a work function that is close to the conduction band of silicon. Each of the PMOS gate electrodes includes a second silicide region on the substrate and a second metal region on the second silicide region. The second silicide region of the PMOS gate electrode consists of a second silicide having a work function that is close to the valence band of silicon.
摘要翻译：双金属CMOS布置及其制造方法提供了形成在衬底上的衬底和多个NMOS器件和PMOS器件。多个NMOS器件和PMOS器件中的每一个具有栅电极。每个NMOS栅极包括衬底上的第一硅化物区域和第一硅化物区域上的第一金属区域。 NMOS栅电极的第一硅化物区域由具有接近硅导带的功函数的第一硅化物组成。每个PMOS栅极电极包括衬底上的第二硅化物区域和第二硅化物区域上的第二金属区域。 PMOS栅电极的第二硅化物区域由具有接近硅的价带的功函数的第二硅化物组成。

44. 发明授权

US07064022B1 Method of forming merged FET inverter/logic gate 有权
标题翻译：形成合并FET逆变器/逻辑门的方法
公开(公告)号：US07064022B1
公开(公告)日：2006-06-20
申请号：US10728844
申请日：2003-12-08
申请人： Wiley Eugene Hill , Ming-Ren Lin , Bin Yu
发明人： Wiley Eugene Hill , Ming-Ren Lin , Bin Yu
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/7854 , H01L21/26586 , H01L21/845 , H01L27/11 , H01L27/1203 , H01L29/66795
摘要： A method forms a semiconductor device from a device that includes a first source region, a first drain region, and a first fin structure that are separated from a second source region, a second drain region, and a second fin structure by an insulating layer. The method may include forming a dielectric layer over the device and removing portions of the dielectric layer to create covered portions and bare portions. The method may also include depositing a gate material over the covered portions and bare portions, doping the first fin structure, the first source region, and the first drain region with a first material, and doping the second fin structure, the second source region, and the second drain region with a second material. The method may further include removing a portion of the gate material over at least one covered portion to form the semiconductor device.
摘要翻译：一种方法从包括通过绝缘层与第二源极区域，第二漏极区域和第二鳍状结构分离的第一源极区域，第一漏极区域和第一鳍状物结构的器件形成半导体器件。该方法可以包括在器件上形成电介质层并去除介电层的部分以产生被覆盖部分和裸露部分。该方法还可以包括在覆盖部分和裸露部分上沉积栅极材料，用第一材料掺杂第一鳍片结构，第一源极区域和第一漏极区域，并掺杂第二鳍片结构，第二源极区域，和具有第二材料的第二漏区。该方法还可以包括在至少一个被覆部分上去除栅极材料的一部分以形成半导体器件。

45. 发明申请

US20050245016A1 Dual-metal CMOS transistors with tunable gate electrode work function and method of making the same 有权
标题翻译：具有可调栅电极功能的双金属CMOS晶体管及其制作方法
公开(公告)号：US20050245016A1
公开(公告)日：2005-11-03
申请号：US10833073
申请日：2004-04-28
申请人： James Pan , Ming-Ren Lin
发明人： James Pan , Ming-Ren Lin
IPC分类号： H01L21/28 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823842
摘要： A dual-metal CMOS arrangement and method of making the same provides a substrate and a plurality of NMOS devices and PMOS devices formed on the substrate. Each of the plurality of NMOS devices and PMOS devices have gate electrodes. Each NMOS gate electrode includes a first silicide region on the substrate and a first metal region on the first silicide region. The first silicide region of the NMOS gate electrode consists of a first silicide having a work function that is close to the conduction band of silicon. Each of the PMOS gate electrodes includes a second silicide region on the substrate and a second metal region on the second silicide region. The second silicide region of the PMOS gate electrode consists of a second silicide having a work function that is close to the valence band of silicon.
摘要翻译：双金属CMOS布置及其制造方法提供了形成在衬底上的衬底和多个NMOS器件和PMOS器件。多个NMOS器件和PMOS器件中的每一个具有栅电极。每个NMOS栅极包括衬底上的第一硅化物区域和第一硅化物区域上的第一金属区域。 NMOS栅电极的第一硅化物区域由具有接近硅导带的功函数的第一硅化物组成。每个PMOS栅极电极包括衬底上的第二硅化物区域和第二硅化物区域上的第二金属区域。 PMOS栅电极的第二硅化物区域由具有接近硅的价带的功函数的第二硅化物组成。

46. 发明授权

US06855989B1 Damascene finfet gate with selective metal interdiffusion 有权
标题翻译：大马士革finfet门与选择性金属相互扩散
公开(公告)号：US06855989B1
公开(公告)日：2005-02-15
申请号：US10674520
申请日：2003-10-01
申请人： Haihong Wang , Shibly S. Ahmed , Ming-Ren Lin , Bin Yu
发明人： Haihong Wang , Shibly S. Ahmed , Ming-Ren Lin , Bin Yu
IPC分类号： H01L21/336 , H01L27/01 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/4908 , H01L29/66795
摘要： A fin field effect transistor includes a fin, a source region, a drain region, a first gate electrode and a second gate electrode. The fin includes a channel. The source region is formed adjacent a first end of the fin and the drain region is formed adjacent a second end of the fin. The first gate electrode includes a first layer of metal material formed adjacent the fin. The second gate electrode includes a second layer of metal material formed adjacent the first layer. The first layer of metal material has a different work function than the second layer of metal material. The second layer of metal material selectively diffuses into the first layer of metal material via metal interdiffusion.
摘要翻译：翅片场效应晶体管包括鳍片，源极区域，漏极区域，第一栅极电极和第二栅极电极。鳍包括一个通道。源区域邻近翅片的第一端形成，并且漏极区域邻近翅片的第二端形成。第一栅电极包括邻近翅片形成的第一金属材料层。第二栅电极包括与第一层相邻形成的第二金属材料层。第一层金属材料具有与第二层金属材料不同的功函数。金属材料的第二层选择性地通过金属相互扩散扩散到金属材料的第一层中。

47. 发明授权

US06833587B1 Heat removal in SOI devices using a buried oxide layer/conductive layer combination 有权
标题翻译：使用掩埋氧化物层/导电层组合的SOI器件中的热去除
公开(公告)号：US06833587B1
公开(公告)日：2004-12-21
申请号：US10174328
申请日：2002-06-18
申请人： Ming-Ren Lin
发明人： Ming-Ren Lin
IPC分类号： H01L2701
CPC分类号： H01L21/76256 , H01L21/84 , Y10S438/928
摘要： A silicon-on-insulator substrate is disclosed which comprises: a silicon substrate layer; a first insulation layer over the silicon substrate layer; a conductive layer over the first insulation layer comprising at least one metal or metal silicide over the first insulation layer; a second insulation layer over the conductive layer; a silicon device layer comprising silicon over the second insulation layer; and at least one conductive plug through the silicon substrate layer and the first insulation layer contacting the conductive layer, or at least one conductive plug through the silicon device layer and the second insulation layer contacting the conductive layer. Also disclosed are methods for making silicon-on-insulator substrates having improved heat transfer structures.
摘要翻译：公开了一种绝缘体上硅衬底，其包括：硅衬底层; 硅衬底层上的第一绝缘层; 所述第一绝缘层上的导电层包括在所述第一绝缘层上的至少一种金属或金属硅化物; 导电层上的第二绝缘层; 在第二绝缘层上包含硅的硅器件层; 以及穿过所述硅衬底层和所述第一绝缘层接触所述导电层的至少一个导电插塞，或通过所述硅器件层和所述第二绝缘层接触所述导电层的至少一个导电插塞。还公开了制造具有改进的传热结构的绝缘体上硅衬底的方法。

48. 发明授权

US06762448B1 FinFET device with multiple fin structures 有权
标题翻译： FinFET器件具有多个鳍结构
公开(公告)号：US06762448B1
公开(公告)日：2004-07-13
申请号：US10405343
申请日：2003-04-03
申请人： Ming-Ren Lin , Haihong Wang , Bin Yu
发明人： Ming-Ren Lin , Haihong Wang , Bin Yu
IPC分类号： H01L2708
CPC分类号： H01L29/785 , H01L21/823412 , H01L21/823437 , H01L27/088 , H01L29/66795 , H01L29/7842
摘要： A semiconductor device includes a group of fin structures. The group of fin structures includes a conductive material and is formed by growing the conductive material in an opening of an oxide layer. The semiconductor device further includes a source region formed at one end of the group of fin structures, a drain region formed at an opposite end of the group of fin structures, and at least one gate.
摘要翻译：半导体器件包括一组翅片结构。翅片结构的组包括导电材料，并且通过在氧化物层的开口中生长导电材料而形成。半导体器件还包括形成在鳍片结构组的一端处的源极区域，形成在鳍片结构组的相对端处的漏极区域和至少一个栅极。

49. 发明授权

US06566212B1 Method of fabricating an integrated circuit with ultra-shallow source/drain extensions 失效
标题翻译：制造具有超浅源/漏扩展的集成电路的方法
公开(公告)号：US06566212B1
公开(公告)日：2003-05-20
申请号：US09761953
申请日：2001-01-17
申请人： Bin Yu , Ming-Ren Lin
发明人： Bin Yu , Ming-Ren Lin
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2255 , H01L29/6656
摘要： A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a solid-phase impurity source. The solid-phase impurity source can be a doped silicon dioxide layer approximately 300 nm thick. The structure is thermally annealed to drive dopants from the solid-phase impurity source into the source and drain regions. The dopants from the impurity source provide ultra-shallow source and drain extensions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).
摘要翻译：制造具有超浅源极/漏极结的集成电路的方法利用固相杂质源。固相杂质源可以是约300nm厚的掺杂二氧化硅层。该结构被热退火以将来自固相杂质源的掺杂剂驱动到源区和漏区。来自杂质源的掺杂剂提供超浅源极和漏极延伸。该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

50. 发明授权

US06531753B1 Embedded conductor for SOI devices using a buried conductive layer/conductive plug combination 失效
标题翻译：使用埋入导电层/导电插头组合的SOI器件的嵌入式导体
公开(公告)号：US06531753B1
公开(公告)日：2003-03-11
申请号：US10174046
申请日：2002-06-18
申请人： Ming-Ren Lin
发明人： Ming-Ren Lin
IPC分类号： H01L2912
CPC分类号： H01L21/76251
摘要： A silicon-on-insulator substrate is disclosed which comprises: a silicon substrate layer; a first insulation layer over the silicon substrate layer; a conductive layer over the first insulation layer comprising at least one metal or metal silicide over the first insulation layer; a second insulation layer over the conductive layer; a silicon device layer comprising silicon over the second insulation layer; at least first conductive plug through the silicon substrate and the first insulation layer contacting the conductive layer; and at least one second conductive plug through the silicon device layer and the second insulation layer contacting the conductive layer. Also disclosed are methods for forming silicon-on-insulator substrates having improved stable ground characteristics.
摘要翻译：公开了一种绝缘体上硅衬底，其包括：硅衬底层; 硅衬底层上的第一绝缘层; 所述第一绝缘层上的导电层包括在所述第一绝缘层上的至少一种金属或金属硅化物; 导电层上的第二绝缘层; 在第二绝缘层上包含硅的硅器件层; 穿过硅衬底的至少第一导电插塞和与导电层接触的第一绝缘层; 以及穿过所述硅器件层和所述第二绝缘层接触所述导电层的至少一个第二导电插塞。还公开了用于形成具有改进的稳定接地特性的绝缘体上硅衬底的方法。

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