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41. 发明申请

US20060131665A1 Method for forming an integrated circuit 有权
标题翻译：集成电路形成方法
公开(公告)号：US20060131665A1
公开(公告)日：2006-06-22
申请号：US11336160
申请日：2006-01-20
申请人： Anand Murthy , Glenn Glass , Andrew Westmeyer , Michael Hattendorf , Tahir Ghani
发明人： Anand Murthy , Glenn Glass , Andrew Westmeyer , Michael Hattendorf , Tahir Ghani
IPC分类号： H01L29/76
CPC分类号： H01L29/7834 , H01L29/665 , H01L29/66636
摘要： A method is described for manufacturing an n-MOS semiconductor transistor. Recesses are formed in a semiconductor substrate adjacent a gate electrode structure. Silicon is embedded in the recesses via a selective epitaxial growth process. The epitaxial silicon is in-situ alloyed with substitutional carbon and in-situ doped with phosphorus. The silicon-carbon alloy generates a uniaxial tensile strain in the channel region between the source and drain, thereby increasing electron channel mobility and the transistor's drive current. The silicon-carbon alloy decreases external resistances by reducing contact resistance between source/drain and silicide regions and by reducing phosphorous diffusivity, thereby permitting closer placement of the transistor's source/drain and channel regions.
摘要翻译：描述了制造n-MOS半导体晶体管的方法。在与栅电极结构相邻的半导体衬底中形成凹部。硅通过选择性外延生长工艺嵌入凹槽中。外延硅与替代原位合金化并原位掺磷。硅碳合金在源极和漏极之间的沟道区域中产生单轴拉伸应变，从而增加电子通道迁移率和晶体管的驱动电流。硅碳合金通过降低源极/漏极和硅化物区域之间的接触电阻并减少磷扩散率来降低外部电阻，从而允许晶体管的源极/漏极和沟道区域更靠近放置。

42. 发明申请

US20060057809A1 Methods for selective deposition to improve selectivity 审中-公开
标题翻译：用于选择性沉积以提高选择性的方法
公开(公告)号：US20060057809A1
公开(公告)日：2006-03-16
申请号：US11270933
申请日：2005-11-10
申请人： Anand Murthy , Nayanee Gupta , Chris Auth , Glenn Glass
发明人： Anand Murthy , Nayanee Gupta , Chris Auth , Glenn Glass
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/823418
摘要： Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.
摘要翻译：描述形成微电子结构的方法和相关装置。那些方法包括提供一种衬底，其包括具有源极和漏极凹部的较高有源面积密度的区域和包括源极和漏极凹陷的较低有源面积密度的区域，其中较低有源面积密度的区域还包括虚设凹槽，并且选择性地沉积源极，漏极和虚拟凹槽中的硅合金层，以增强硅合金沉积的选择性和均匀性。

43. 发明申请

US20050272187A1 Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby 有权
标题翻译：包含EPI硅尖端和由此制成的制品的超薄体SOI器件的工艺
公开(公告)号：US20050272187A1
公开(公告)日：2005-12-08
申请号：US11204418
申请日：2005-08-15
申请人： Anand Murthy , Brian Doyle , Jack Kavalieros , Robert Chau
发明人： Anand Murthy , Brian Doyle , Jack Kavalieros , Robert Chau
IPC分类号： H01L21/336 , H01L29/417 , H01L29/786
CPC分类号： H01L29/41733 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/66772 , H01L29/78618
摘要： The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.
摘要翻译：本发明涉及一种晶体管，其包括超薄体外延层，该超薄体外延层与具有由晶体管的栅极堆叠下方的底切指定的沟道的沟道形成嵌入的结。本发明还涉及一种形成晶体管的方法和涉及晶体管的系统。

44. 发明授权

US06621131B2 Semiconductor transistor having a stressed channel 有权
公开(公告)号：US06621131B2
公开(公告)日：2003-09-16
申请号：US10002465
申请日：2001-11-01
申请人： Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
发明人： Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
IPC分类号： H01L2976
CPC分类号： H01L29/7848 , H01L21/823814 , H01L27/092 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7842
摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

45. 发明授权

US06214679B1 Cobalt salicidation method on a silicon germanium film 有权
标题翻译：硅锗膜上的钴盐化法
公开(公告)号：US06214679B1
公开(公告)日：2001-04-10
申请号：US09476393
申请日：1999-12-30
申请人： Anand Murthy , Robert S. Chau
发明人： Anand Murthy , Robert S. Chau
IPC分类号： H01L21336
CPC分类号： H01L29/66636 , H01L21/28052 , H01L21/28518 , H01L21/28525 , H01L21/28562 , H01L29/045 , H01L29/165 , H01L29/41783 , H01L29/456 , H01L29/4941 , H01L29/665
摘要： A method of forming a cobalt germanosilicide film is described. According to the present invention a silicon germanium alloy is formed on a substrate. A cobalt film is then formed on the silicon germanium alloy. The substrate is then heated to a temperature of greater than 850° C. for a period of time less than 20 seconds to form a cobalt germanium silicide film.
摘要翻译：描述形成锗硅酸钴膜的方法。根据本发明，在基板上形成硅锗合金。然后在硅锗合金上形成钴膜。然后将衬底加热至大于850℃的温度一段时间少于20秒以形成锗化锗硅化物膜。

46. 发明申请

US20110186912A1 TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER 有权
标题翻译：具有导体材料层的晶体管栅极电极
公开(公告)号：US20110186912A1
公开(公告)日：2011-08-04
申请号：US13082305
申请日：2011-04-07
申请人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
发明人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
IPC分类号： H01L29/772 , H01L27/092
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
摘要翻译：本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

47. 发明申请

US20110018031A1 TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER 有权
公开(公告)号：US20110018031A1
公开(公告)日：2011-01-27
申请号：US12893983
申请日：2010-09-29
申请人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
发明人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

48. 发明授权

US07812394B2 CMOS transistor junction regions formed by a CVD etching and deposition sequence 有权
标题翻译：通过CVD蚀刻和沉积顺序形成CMOS晶体管结区域
公开(公告)号：US07812394B2
公开(公告)日：2010-10-12
申请号：US12250191
申请日：2008-10-13
申请人： Anand Murthy , Glenn A. Glass , Andrew N. Westmeyer , Michael L. Hattendorf , Jeffrey R. Wank
发明人： Anand Murthy , Glenn A. Glass , Andrew N. Westmeyer , Michael L. Hattendorf , Jeffrey R. Wank
IPC分类号： H01L31/119
CPC分类号： H01L29/7848 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/517 , H01L29/66628 , H01L29/7834
摘要： This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.
摘要翻译：本发明增加了替代源极 - 漏极cMOS晶体管的技术。方法可以包括使用一个设备组来蚀刻衬底材料中的凹部，然后在另一个设备组中进行沉积。公开了一种在没有大气暴露的情况下在相同的反应器中进行蚀刻和随后的沉积的方法。用于替代源极 - 漏极应用的源极 - 漏极凹槽的原位蚀刻提供了优于现有技术的非原位蚀刻的几个优点。晶体管驱动电流通过以下因素得到改善：（1）当被蚀刻的表面暴露于大气中时，消除硅 - 外延层界面的污染，（2）精确控制蚀刻凹槽的形状。沉积可以通过各种技术进行，包括选择性和非选择性方法。在覆盖层沉积的情况下，还提出了避免在性能关键区域中无定形沉积的措施。

49. 发明授权

US07663192B2 CMOS device and method of manufacturing same 有权
标题翻译： CMOS器件及其制造方法
公开(公告)号：US07663192B2
公开(公告)日：2010-02-16
申请号：US12215989
申请日：2008-06-30
申请人： Bernhard Sell , Anand Murthy , Mark Liu , Daniel Aubertine
发明人： Bernhard Sell , Anand Murthy , Mark Liu , Daniel Aubertine
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823835 , H01L29/66628 , H01L29/7834
摘要： A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.
摘要翻译： CMOS器件包括NMOS（110）和PMOS（130）晶体管，每个晶体管包括限定栅极绝缘体平面（150,170）的栅电极（111,131）和栅极绝缘体（112,132）。晶体管每个还包括具有栅极绝缘体平面下方的第一部分（115,135）和栅极绝缘体平面上方的第二部分（116,136）的源/漏区（113/114,133 / 134）绝缘材料（117）。 NMOS晶体管还包括阻挡层（121），其具有在栅电极和源极触点（118）之间的部分（122）和栅极电极和漏极触点（119）之间的部分（123）。所述PMOS晶体管还包括阻挡层（141），所述阻挡层（141）具有在所述源极区域和所述绝缘材料之间的部分（142）以及所述漏极区域和所述绝缘材料之间的部分（143）。

50. 发明授权

US07473947B2 Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby 有权
标题翻译：包含EPI硅尖端和由此制成的制品的超薄体SOI器件的工艺
公开(公告)号：US07473947B2
公开(公告)日：2009-01-06
申请号：US10194506
申请日：2002-07-12
申请人： Anand Murthy , Brian Doyle , Jack Kavalieros , Robert Chau
发明人： Anand Murthy , Brian Doyle , Jack Kavalieros , Robert Chau
IPC分类号： H01L21/00
CPC分类号： H01L29/41733 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/66772 , H01L29/78618
摘要： The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.
摘要翻译：本发明涉及一种晶体管，其包括超薄体外延层，该超薄体外延层与具有由晶体管的栅极堆叠下方的底切指定的沟道的沟道形成嵌入的结。本发明还涉及一种形成晶体管的方法以及结合晶体管的系统。

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