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41. 发明申请

US20120061034A1 Slim Bottom Bar Wedge Lock 审中-公开
标题翻译：细长条形楔形锁
公开(公告)号：US20120061034A1
公开(公告)日：2012-03-15
申请号：US12880268
申请日：2010-09-13
申请人： Philip Ng
发明人： Philip Ng
IPC分类号： E06B9/42
CPC分类号： E06B9/17046 , E06B9/42
摘要： There is disclosed a bottom bar for attachment to a lower edge of a window blind. The bottom bar includes an elongated tube having a bottom and a pair of opposing side walls separated by a space and an elongated slit extending along the tube, the slit communicating with the space. The slit is dimensioned to permit the lower edge of the window blind to pass through. The bottom bar further includes an elongated lock member dimensioned to fit within the space, the elongated lock member dimensioned to be too small to pass through the slit. The lock member has a flat side wall for attachment to the lower edge of the window blind by an adhesive. The opposing side walls of the elongated tube are tapered toward each other from the bottom towards the slit such that the opposing side walls abut the flat side wall of the lock member when the lock member moves towards the slit.
摘要翻译：公开了一种用于附接到窗帘的下边缘的底部杆。底杆包括细长管，其具有底部和由空间隔开的一对相对侧壁和沿着管延伸的细长狭缝，狭缝与空间连通。狭缝的尺寸被设计成允许窗帘的下边缘通过。底部杆还包括尺寸适于安装在该空间内的细长锁定构件，该细长锁定构件的尺寸设计得太小而不能通过狭缝。锁定构件具有平坦的侧壁，用于通过粘合剂附接到窗帘的下边缘。细长管的相对侧壁从底部朝向狭缝彼此逐渐变细，使得当锁定构件向狭缝移动时，相对的侧壁邻接锁定构件的平坦侧壁。

42. 发明申请

US20110219190A1 CACHE WITH RELOAD CAPABILITY AFTER POWER RESTORATION 有权
标题翻译：电源恢复后具有重新启动能力的缓存
公开(公告)号：US20110219190A1
公开(公告)日：2011-09-08
申请号：US12716391
申请日：2010-03-03
申请人： Philip Ng , Jimshed B. Mirza , Anthony Asaro
发明人： Philip Ng , Jimshed B. Mirza , Anthony Asaro
IPC分类号： G06F12/08 , G06F1/24
CPC分类号： G06F12/0862 , G06F12/0868 , G06F2212/1028 , G06F2212/6024 , Y02D10/13
摘要： A method and apparatus for repopulating a cache are disclosed. At least a portion of the contents of the cache are stored in a location separate from the cache. Power is removed from the cache and is restored some time later. After power has been restored to the cache, it is repopulated with the portion of the contents of the cache that were stored separately from the cache.
摘要翻译：公开了一种用于重新填充缓存的方法和装置。缓存的内容的至少一部分被存储在与高速缓存分开的位置。电源从缓存中删除，并在稍后恢复。在电源恢复到缓存之后，它将重新填充与高速缓存单独存储的高速缓存的内容部分。

43. 发明申请

US20110114809A1 Mounting Bracket for Blind 审中-公开
标题翻译：盲装安装支架
公开(公告)号：US20110114809A1
公开(公告)日：2011-05-19
申请号：US12621731
申请日：2009-11-19
申请人： Philip Ng
发明人： Philip Ng
IPC分类号： F16M13/00
CPC分类号： E06B9/42 , E06B9/323
摘要： The invention is a fascia and mounting bracket combination for a blind having a head portion. The mounting bracket and fascia combination includes a mounting bracket having a first locking element and a fascia having a face portion and an extended leg. The extended leg has a proximal end adjacent the face portion and a distal end opposite the proximal end. The fascia and bracket combination further includes a second locking element formed on the fascia adjacent the distal end of the extended leg, the second locking element configured to mate with the first locking element. A release member is mounted to the mounting bracket adjacent the first locking element, the release member movable between a locked position wherein the release member is clear of the second locking element, and a release position wherein the release member bears against the second locking element sufficiently to disengage the second locking element from the first locking element.
摘要翻译：本发明是一种用于具有头部的盲板的面板和安装支架组合件。安装支架和面板组合包括具有第一锁定元件和具有面部部分和延伸腿部的面板的安装支架。延伸腿具有邻近面部部分的近端和与近端相对的远端。面板和支架组合还包括形成在邻近延伸腿的远端的面板上的第二锁定元件，第二锁定元件被配置为与第一锁定元件配合。释放构件与第一锁定元件相邻地安装到安装支架上，释放构件可在释放构件离开第二锁定元件的锁定位置和释放位置之间移动，释放构件能够充分抵靠第二锁定元件以使第二锁定元件从第一锁定元件脱离。

44. 外观设计

USD633742S1 Bottom bar for use with a fabric blind 有权
标题翻译：用于织物盲人的底部条
公开(公告)号：USD633742S1
公开(公告)日：2011-03-08
申请号：US29353528
申请日：2010-01-11
申请人： Philip Ng
设计人： Philip Ng

45. 发明申请

US20090096501A1 APPARATUS AND METHOD FOR PREVENTING SNAP BACK IN INTEGRATED CIRCUITS 有权
标题翻译：用于防止集成电路中的反馈的装置和方法
公开(公告)号：US20090096501A1
公开(公告)日：2009-04-16
申请号：US11870322
申请日：2007-10-10
申请人： Philip Ng , Sai Kai Tsang , Kris Li , Liqi Wang , Jinshu Son
发明人： Philip Ng , Sai Kai Tsang , Kris Li , Liqi Wang , Jinshu Son
IPC分类号： H03K3/356
CPC分类号： H03K3/356182 , H03K3/013
摘要： A method for preventing snap-back in a circuit including at least one MOS transistor having a parasitic bipolar transistor associated with it includes coupling a circuit node including at least one source/drain node of the at least one MOS transistor to a bias-voltage circuit and enabling the bias-voltage circuit to supply a potential to the at least one source/drain node of the at least on MOS transistor, the potential having a magnitude selected to prevent the parasitic bipolar transistor from turning on.
摘要翻译：一种用于防止在包括至少一个具有与其相关联的寄生双极晶体管的MOS晶体管的电路中的回耦的方法包括将包括至少一个MOS晶体管的至少一个源极/漏极节点的电路节点耦合到偏置电压电路以及使所述偏置电压电路向所述至少一个MOS晶体管的所述至少一个源极/漏极节点提供电位，所述电位具有选择的幅度以防止所述寄生双极晶体管导通。

46. 发明授权

US07304514B2 Methods and circuits for sensing on-chip voltage in powerup mode 有权
标题翻译：用于在上电模式下检测片上电压的方法和电路
公开(公告)号：US07304514B2
公开(公告)日：2007-12-04
申请号：US11399848
申请日：2006-04-06
申请人： Johnny Chan , Philip Ng
发明人： Johnny Chan , Philip Ng
IPC分类号： H03L7/00
CPC分类号： H03K5/24
摘要： A method for sensing voltage on an internal node in an integrated circuit includes applying a voltage larger than a threshold value to a first pad, generating from the activation voltage a potential for a sensing circuit and coupled to the internal node, and coupling an output of the sensing circuit to a second pad on the integrated circuit when the activation voltage is present on the first pad. A sensing circuit includes first and second pads, a voltage-sensor circuit having an input coupled to an internal node and a power connection coupled to a sensor power node. A circuit is configured to place a supply potential on the sensor power node when a threshold value is on the first pad. A switch coupled between the sensing circuit and the second pad turns on when the supply potential is on the voltage sensor power node.
摘要翻译：用于感测集成电路中的内部节点上的电压的方法包括将大于阈值的电压施加到第一焊盘，从激活电压产生感测电路的电位并耦合到内部节点，并将当激活电压存在于第一焊盘上时，感测电路连接到集成电路上的第二焊盘。感测电路包括第一和第二焊盘，具有耦合到内部节点的输入的电压传感器电路和耦合到传感器功率节点的电力连接。电路被配置为当阈值位于第一焊盘上时，在传感器电源节点上放置电源。当电源位于电压传感器功率节点上时，耦合在感测电路和第二焊盘之间的开关导通。

47. 发明申请

US20070250652A1 HIGH SPEED DUAL-WIRE COMMUNICATIONS DEVICE REQUIRING NO PASSIVE PULLUP COMPONENTS 审中-公开
标题翻译：高速双线通信设备，不需要无源PULLUP COMPONENTS
公开(公告)号：US20070250652A1
公开(公告)日：2007-10-25
申请号：US11379872
申请日：2006-04-24
申请人： Philip Ng , Jinshu Son
发明人： Philip Ng , Jinshu Son
IPC分类号： G06F13/00
CPC分类号： G06F13/4077 , G06F2213/0016
摘要： A dual-wire communications bus circuit, compatible with existing two-wire protocols, includes a first and second part of the communications bus circuit to couple to a communications bus. The bus has a first line for carrying data signals from a master device to a slave device and a second line to carry a clock signal between the devices. To improve data throughout and reduce noise, an active pullup device is located in at least one part of the communications bus circuit, the active pullup device in the first part of the of the communications bus circuit couples to the first line and an optional active pullup device in the second part couples to the second line of the communications bus. Each active pullup device may provide a high logic level on one of the communications bus lines.
摘要翻译：与现有的双线协议兼容的双线通信总线电路包括通信总线电路的第一和第二部分以耦合到通信总线。总线具有用于承载从主设备到从设备的数据信号的第一行，以及用于在设备之间携带时钟信号的第二行。为了改善数据并减少噪声，有源上拉器件位于通信总线电路的至少一部分中，通信总线电路的第一部分中的有源上拉器件耦合到第一条线路，并且可选的有源上拉电路第二部分中的设备耦合到通信总线的第二行。每个有源上拉装置可以在通信总线之一上提供高逻辑电平。

48. 发明申请

US20070237013A1 Indirect measurement of negative margin voltages in endurance testing of EEPROM cells 有权
标题翻译：在EEPROM单元的耐久性测试中间接测量负余量电压
公开(公告)号：US20070237013A1
公开(公告)日：2007-10-11
申请号：US11393551
申请日：2006-03-29
申请人： Philip Ng , Minh Le , Liqi Wang , Jinshu Son
发明人： Philip Ng , Minh Le , Liqi Wang , Jinshu Son
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C16/04 , G11C29/50004
摘要： An electronic test structure and method for testing non-volatile memory cells. The structure includes a first transistor coupled in series to a floating gate transistor whereby a source of the first transistor is coupled to a positive power supply voltage and a source of the floating gate transistor is coupled to a power supply ground. A gate of the first transistor is further coupled to a source of the first transistor. A second transistor is coupled in series with a memory cell with a source of the second transistor coupled to a positive power supply voltage and a gate of the second transistor is coupled to the drain of the first transistor.
摘要翻译：用于测试非易失性存储单元的电子测试结构和方法。该结构包括与浮栅晶体管串联耦合的第一晶体管，由此第一晶体管的源极耦合到正电源电压，并且浮栅晶体管的源极耦合到电源地。第一晶体管的栅极进一步耦合到第一晶体管的源极。第二晶体管与存储单元串联耦合，其中第二晶体管的源极耦合到正电源电压，第二晶体管的栅极耦合到第一晶体管的漏极。

49. 发明申请

US20070236259A1 METHOD AND CIRCUITS FOR SENSING ON-CHIP VOLTAGE IN POWERUP MODE 有权
标题翻译：用于在电源模式下感测片上电压的方法和电路
公开(公告)号：US20070236259A1
公开(公告)日：2007-10-11
申请号：US11399848
申请日：2006-04-06
申请人： Johnny Chan , Philip Ng
发明人： Johnny Chan , Philip Ng
IPC分类号： H03K5/22
CPC分类号： H03K5/24
摘要： A method for sensing voltage on an internal node in an integrated circuit includes applying a voltage larger than a threshold value to a first pad, generating from the activation voltage a potential for a sensing circuit and coupled to the internal node, and coupling an output of the sensing circuit to a second pad on the integrated circuit when the activation voltage is present on the first pad. A sensing circuit includes first and second pads, a voltage-sensor circuit having an input coupled to an internal node and a power connection coupled to a sensor power node. A circuit is configured to place a supply potential on the sensor power node when a threshold value is on the first pad. A switch coupled between the sensing circuit and the second pad turns on when the supply potential is on the voltage sensor power node.
摘要翻译：用于感测集成电路中的内部节点上的电压的方法包括将大于阈值的电压施加到第一焊盘，从激活电压产生感测电路的电位并耦合到内部节点，并将当激活电压存在于第一焊盘上时，感测电路连接到集成电路上的第二焊盘。感测电路包括第一和第二焊盘，具有耦合到内部节点的输入的电压传感器电路和耦合到传感器功率节点的电力连接。电路被配置为当阈值位于第一焊盘上时，在传感器电源节点上放置电源。当电源位于电压传感器功率节点上时，耦合在感测电路和第二焊盘之间的开关导通。

50. 发明申请

US20070121384A1 Method and apparatus for implementing walkout of device junctions 有权
标题翻译：用于实现设备路口迂回的方法和装置
公开(公告)号：US20070121384A1
公开(公告)日：2007-05-31
申请号：US11291498
申请日：2005-11-30
申请人： Philip Ng , Jinshu Son , Johnny Chan
发明人： Philip Ng , Jinshu Son , Johnny Chan
IPC分类号： G11C11/34
CPC分类号： G11C5/145 , G11C5/147
摘要： A high-voltage charge pump circuit includes a charge pump circuit. A first high-voltage output circuit is configured to set an output voltage of the charge pump at a first voltage level selected for regular programming and erasing memory cells. A second high-voltage output circuit is configured to set the output voltage of the charge pump at a second voltage level selected for walkout of device junctions, the second voltage level being higher than the first voltage level. A third high-voltage output circuit is configured to set the output voltage of the charge pump at a third voltage level selected for guardband programming and erasing, the third voltage level being lower than the second voltage level and higher than the first voltage level. Selection circuitry selectively couples one of the first, second, and third high-voltage output circuits to the output of the high-voltage charge pump circuit.
摘要翻译：高压电荷泵电路包括电荷泵电路。第一高压输出电路被配置为将电荷泵的输出电压设置为为常规编程而选择的第一电压电平并擦除存储器单元。第二高电压输出电路被配置为将电荷泵的输出电压设置为选择用于器件结的迂回的第二电压电平，第二电压电平高于第一电压电平。第三高压输出电路被配置为将电荷泵的输出电压设置为选择用于保护带编程和擦除的第三电压电平，第三电压电平低于第二电压电平并高于第一电压电平。选择电路将第一，第二和第三高压输出电路中的一个选择性地耦合到高压电荷泵电路的输出。

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