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41. 发明申请

US20120217625A1 INTEGRATED CIRCUIT MICRO-MODULE 有权
标题翻译：集成电路微型模块
公开(公告)号：US20120217625A1
公开(公告)日：2012-08-30
申请号：US13467259
申请日：2012-05-09
申请人： Anuraag Mohan , Peter Smeys
发明人： Anuraag Mohan , Peter Smeys
IPC分类号： H01L25/065 , H01L23/66
CPC分类号： H01L24/97 , H01L21/4853 , H01L21/486 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3121 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5385 , H01L23/5389 , H01L23/66 , H01L24/24 , H01L24/82 , H01L25/0652 , H01L25/16 , H01L2221/68377 , H01L2223/6677 , H01L2224/24137 , H01L2224/24227 , H01L2224/2518 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01087 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H05K1/165 , H05K1/185 , H05K2201/10098 , H05K2203/1469 , H01L2224/82 , H01L2924/00
摘要： One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna.
摘要翻译：本发明的一个方面涉及一种集成电路封装，其包括在衬底上形成的多层平坦化，可光成像环氧树脂。在一些设计中，衬底是硅晶片。集成电路嵌入在环氧树脂中。通过互连层电耦合到集成电路的有源面的天线在一个环氧树脂层上形成。在各种实施例中，环氧树脂层中的至少一些位于衬底和天线之间，使得在衬底和天线之间存在至少约100微米的距离。

42. 发明申请

US20110272780A1 METHOD AND STRUCTURE FOR IMPROVING THE QUALILTY FACTOR OF RF INDUCTORS 审中-公开
标题翻译：改进射频电感器质量因子的方法和结构
公开(公告)号：US20110272780A1
公开(公告)日：2011-11-10
申请号：US12774532
申请日：2010-05-05
申请人： Peter Smeys , Kyuwoon Hwang , Peter J. Hopper , William French
发明人： Peter Smeys , Kyuwoon Hwang , Peter J. Hopper , William French
IPC分类号： H01L29/86 , H01L21/02
CPC分类号： H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： An on-chip inductor structure is formed as part of an integrated circuit structure. The integrate circuit structure includes a semiconductor substrate having a top side and a back side, integrated circuit elements formed on the top side of the substrate, a conductive interconnect structure formed in contact with the integrated circuit elements and a passivation layer formed over the integrated circuit elements. The inductor structure comprises a layer of photoimageable epoxy formed on the passivation layer, a conductive inductor coil formed on the layer of photoimageable epoxy and at least one conductive via that extends from the inductor coil to the interconnect layer to provide electrical connection therebetween. Additionally, a back side trench may be formed in the back side of the semiconductor substrate beneath the inductor coil.
摘要翻译：片上电感器结构形成为集成电路结构的一部分。集成电路结构包括具有顶侧和背面的半导体衬底，形成在衬底的顶侧上的集成电路元件，与集成电路元件接触形成的导电互连结构和形成在集成电路上的钝化层元素。电感器结构包括形成在钝化层上的可光成像环氧树脂层，形成在可光成像环氧树脂层上的导电电感线圈和从电感线圈延伸到互连层的至少一个导电通孔，以在它们之间提供电连接。此外，可以在电感线圈下方的半导体衬底的背面形成背面沟槽。

43. 发明授权

US07936246B2 On-chip inductor for high current applications 有权
标题翻译：用于大电流应用的片上电感
公开(公告)号：US07936246B2
公开(公告)日：2011-05-03
申请号：US11973536
申请日：2007-10-09
申请人： Peter J. Hopper , Peter Smeys , Andrei Papou
发明人： Peter J. Hopper , Peter Smeys , Andrei Papou
IPC分类号： H01F27/24
CPC分类号： H01F17/0013 , H01F3/14 , H01F27/34 , H01F41/046 , H01F2017/0066 , Y10T29/49078
摘要： Saturation of nonlinear ferromagnetic core material for on-chip inductors for high current applications is significantly reduced by providing a core design wherein magnetic flux does not form a closed loop, but rather splits into multiple sub-fluxes that are directed to cancel each other. The design enables high on-chip inductance for high current power applications.
摘要翻译：用于大电流应用的片上电感器的非线性铁磁芯材料的饱和度通过提供其中磁通量不形成闭环但是分成多个子通量的核心设计而显着降低，这些子通量被引导以相互抵消。该设计可实现高电流功率应用的高片内电感。

44. 发明授权

US07461305B1 System and method for detecting and preventing race condition in circuits 有权
标题翻译：用于检测和防止电路中竞争条件的系统和方法
公开(公告)号：US07461305B1
公开(公告)日：2008-12-02
申请号：US11115632
申请日：2005-04-26
申请人： Edgardo F. Klass , Peter Smeys
发明人： Edgardo F. Klass , Peter Smeys
IPC分类号： G06K5/04
CPC分类号： G01R31/3016
摘要： A system and method for detecting and preventing race conditions in a circuit is provided. The system includes a first memory element for receiving a data stream. The system further includes a plurality of additional memory elements for directly receiving an output of the data stream from the first memory element. Delay elements are defined between the first memory element and the plurality of additional memory elements other than a second memory element, so that each delay element between the first memory element and the plurality of additional memory elements other than the second memory element are combined to define a sum delay. A plurality of comparators are connected to the plurality of memory elements such that each comparator being configured to compare an input to the first memory element and an output of each of the plurality of additional memory elements. The output from the comparator helps to identify whether a race condition is present between the first memory element and any one of the plurality of additional memory elements.
摘要翻译：提供一种用于检测和防止电路中的竞争条件的系统和方法。该系统包括用于接收数据流的第一存储元件。该系统还包括多个附加存储器元件，用于直接从第一存储器元件接收数据流的输出。在第一存储器元件和除第二存储器元件之外的多个附加存储器元件之间定义延迟元件，使得第一存储器元件与除第二存储器元件之外的多个附加存储器元件之间的每个延迟元件被组合以定义总和延迟。多个比较器连接到多个存储器元件，使得每个比较器被配置为将输入与第一存储器元件和多个附加存储元件中的每一个的输出进行比较。比较器的输出有助于识别在第一存储器元件和多个附加存储器元件中的任何一个之间是否存在竞争条件。

45. 发明授权

US09331137B1 Metal-insulator-metal capacitors between metal interconnect layers 有权
标题翻译：金属互连层之间的金属 - 绝缘体 - 金属电容器
公开(公告)号：US09331137B1
公开(公告)日：2016-05-03
申请号：US13431818
申请日：2012-03-27
申请人： Deepa Ratakonda , Peter Smeys , Shuxian Chen , Girish Venkitachalam
发明人： Deepa Ratakonda , Peter Smeys , Shuxian Chen , Girish Venkitachalam
IPC分类号： H01L29/06 , H01L49/02 , H01L27/108
CPC分类号： H01L28/60 , H01L23/5223 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit may include interconnects formed from alternating metal interconnect layers and inter-metal dielectric layers. A metal-insulator-metal capacitor may be formed within a selected inter-metal dielectric layer. The metal-insulator-metal capacitor may include first and second capacitor electrodes. The first capacitor electrode may contact a first conductive interconnect line in an underlying metal interconnect layer. The second capacitor electrode may overlap the first capacitor electrode and a portion of a second conductive interconnect line in the underlying metal layer. A via may be formed between the underlying metal interconnect layer and an additional metal interconnect layer. The via may simultaneously contact the second capacitor electrode and the second conductive interconnect line.
摘要翻译：集成电路可以包括由交替的金属互连层和金属间介电层形成的互连。可以在所选择的金属间介电层内形成金属 - 绝缘体 - 金属电容器。金属 - 绝缘体 - 金属电容器可包括第一和第二电容器电极。第一电容器电极可以接触下面的金属互连层中的第一导电互连线。第二电容器电极可以与第一电容器电极和下面的金属层中的第二导电互连线的一部分重叠。可以在下面的金属互连层和另外的金属互连层之间形成通孔。通孔可以同时接触第二电容器电极和第二导电互连线。

46. 发明授权

US08390093B1 System and method of galvanic isolation in digital signal transfer integrated circuits utilizing conductivity modulation of semiconductor substrate 有权
标题翻译：利用半导体衬底的电导率调制的数字信号传输集成电路中的电流隔离的系统和方法
公开(公告)号：US08390093B1
公开(公告)日：2013-03-05
申请号：US13230171
申请日：2011-09-12
申请人： Peter J. Hopper , Peter Smeys , William French , Andrei Papou , Aditi Dutt Chaudhuri
发明人： Peter J. Hopper , Peter Smeys , William French , Andrei Papou , Aditi Dutt Chaudhuri
IPC分类号： H01L21/70 , H01L21/00 , H04B1/44
CPC分类号： H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A galvanic isolation system provides galvanic isolation in digital transfer integrated circuits by using conductivity modulation of the semiconductor substrate. Modulation of the conductivity of the substrate affects eddy current losses of a (differential) RF inductor that is isolated from the substrate by a sufficient amount of dielectric material, which provides a basis for signal transfer from the modulated substrate to the inductor across the isolation barrier.
摘要翻译：电隔离系统通过使用半导体衬底的电导率调制在数字传输集成电路中提供电隔离。衬底的导电性的调制影响了通过足够量的电介质材料与衬底隔离的（差分）RF电感器的涡电流损耗，这提供了通过隔离屏障从调制衬底到电感器的信号传递的基础。

47. 发明授权

US08338913B2 Semiconductor inductor with a serpentine shaped conductive wire interlaced with a serpentine shaped ferromagnetic core 有权
标题翻译：具有蛇形导电线的半导体电感器与蛇形铁磁芯线交织
公开(公告)号：US08338913B2
公开(公告)日：2012-12-25
申请号：US12943391
申请日：2010-11-10
申请人： Peter Smeys , Andrei Papou , Peter J. Hopper
发明人： Peter Smeys , Andrei Papou , Peter J. Hopper
IPC分类号： H01L29/82
CPC分类号： H01L28/10 , H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/00
摘要： The inductance of an inductor is increased by forming a conductive wire to have a serpentine shape that weaves through a ferromagnetic core that has a number of segments that are connected together in a serpentine shape where each segment of the ferromagnetic core also has a number of sections that are connected together in a serpentine shape.
摘要翻译：电感器的电感通过形成导线而增加，其具有蛇形形状，该蛇形形状通过铁磁芯编织，所述铁磁芯具有以蛇形形式连接在一起的多个段，其中铁磁芯的每个段也具有多个部分它们以蛇形形状连接在一起。

48. 发明申请

US20110163457A1 INTEGRATED CIRCUIT MICRO-MODULE 有权
标题翻译：集成电路微型模块
公开(公告)号：US20110163457A1
公开(公告)日：2011-07-07
申请号：US13022392
申请日：2011-02-07
申请人： Anuraag Mohan , Peter Smeys
发明人： Anuraag Mohan , Peter Smeys
IPC分类号： H01L23/50 , H01L21/50
CPC分类号： H01L24/97 , H01L21/4853 , H01L21/486 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3121 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5385 , H01L23/5389 , H01L23/66 , H01L24/24 , H01L24/82 , H01L25/0652 , H01L25/16 , H01L2221/68377 , H01L2223/6677 , H01L2224/24137 , H01L2224/24227 , H01L2224/2518 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01087 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H05K1/165 , H05K1/185 , H05K2201/10098 , H05K2203/1469 , H01L2224/82 , H01L2924/00
摘要： One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna.
摘要翻译：本发明的一个方面涉及一种集成电路封装，该集成电路封装包括在衬底上形成的多层平坦化，光可成像环氧树脂。在一些设计中，衬底是硅晶片。集成电路嵌入在环氧树脂中。通过互连层电耦合到集成电路的有源面的天线在一个环氧树脂层上形成。在各种实施例中，环氧树脂层中的至少一些位于衬底和天线之间，使得在衬底和天线之间存在至少约100微米的距离。

49. 发明授权

US06653710B2 Fuse structure with thermal and crack-stop protection 失效
公开(公告)号：US06653710B2
公开(公告)日：2003-11-25
申请号：US09788077
申请日：2001-02-16
申请人： James W. Adkisson , Edward Maciejewski , Peter Smeys , Anthony K. Stamper
发明人： James W. Adkisson , Edward Maciejewski , Peter Smeys , Anthony K. Stamper
IPC分类号： H01L2900
CPC分类号： H01L23/5329 , H01L23/3735 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Thermal degradation of a low-k organic dielectric material is avoided or limited in the proximity of a heat source such as a fusible element by overlaying the low-k material with a thermally conductive material and providing a low thermal resistance path from the thermally conductive material, possibly having a low modulus of elasticity, to a heat sink. The thermally conductive material thus provides crack-stop protection for further layers of an integrated circuit or interconnect structure above the fusible element by mechanical, chemical and thermal encapsulation of the heat source and low-k material.

50. 发明申请

US20110310579A1 Inductive Structure and Method of Forming the Inductive Structure with an Attached Core Structure 有权
标题翻译：电感结构和形成具有附加芯结构的感应结构的方法
公开(公告)号：US20110310579A1
公开(公告)日：2011-12-22
申请号：US12816788
申请日：2010-06-16
申请人： Peter Smeys , Andrei Papou
发明人： Peter Smeys , Andrei Papou
IPC分类号： H01F27/28 , H05K7/02 , H05K3/32 , H01F27/24
CPC分类号： H01F17/0013 , H01F17/04 , H01F27/26 , H01F41/046 , H01F2017/0086 , H01F2027/2819 , H01L23/5227 , H01L23/645 , H01L2924/0002 , Y10T29/4902 , Y10T29/49073 , Y10T29/4913 , H01L2924/00
摘要： An inductor is formed on a wafer by attaching a first core structure to the wafer with a pick and place operation, forming a coil with one or more thick metal layers over the first core structure, and then attaching a second core structure to the first core structure with the pick and place operation after the coil has been formed. In addition, the pick and place operation can also be used to attach one or more integrated circuits to the wafer to form an integrated inductive device.
摘要翻译：通过利用拾取和放置操作将第一芯结构附接到晶片，在晶片上形成电感器，在第一芯结构上形成具有一个或多个厚金属层的线圈，然后将第二芯结构附接到第一芯线圈已经形成后的拾取和放置操作的结构。此外，拾取和放置操作也可以用于将一个或多个集成电路连接到晶片以形成集成的电感器件。

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