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41. 发明申请

US20140078808A1 Embedded Nonvolatile Memory Elements Having Resistive Switching Characteristics 有权
标题翻译：具有电阻开关特性的嵌入式非易失性存储器元件
公开(公告)号：US20140078808A1
公开(公告)日：2014-03-20
申请号：US13621371
申请日：2012-09-17
申请人： Imran Hashim , Tony Chiang , Vidyut Gopal , Yun Wang
发明人： Imran Hashim , Tony Chiang , Vidyut Gopal , Yun Wang
IPC分类号： H01L27/24 , G11C11/21
CPC分类号： H01L45/1608 , G11C13/0007 , G11C13/0069 , G11C2213/32 , G11C2213/51 , G11C2213/52 , G11C2213/74 , G11C2213/79 , H01L27/2436 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.
摘要翻译：提供了各自包括电阻式开关层和电流控制元件的非易失性存储器组件。转向元件可以是与开关层串联连接的晶体管。由转向元件提供的电阻控制允许使用需要低开关电压和电流的开关层。包括这种开关层的存储器组件比例如需要高得多的开关电压的闪速存储器更容易嵌入到具有其它低电压组件（例如逻辑和数字信号处理组件）的集成电路芯片中。在一些实施例中，所提供的非易失性存储器组件在小于约3.0V的开关电压和小于50微安的相应电流下工作。存储元件可以包括设置在氮化钛电极和掺杂多晶硅电极之间的富含金属的氧化铪。一个电极可以连接到晶体管的漏极或源极，而另一个电极连接到信号线。

42. 发明申请

US20130107604A1 Method for Forming Resistive Switching Memory Elements with Improved Switching Behavior 有权
标题翻译：用于形成具有改进的开关行为的电阻式开关存储元件的方法
公开(公告)号：US20130107604A1
公开(公告)日：2013-05-02
申请号：US13281777
申请日：2011-10-26
申请人： Yun Wang , Tony Chiang , Imran Hashim , Vidyut Gopal
发明人： Yun Wang , Tony Chiang , Imran Hashim , Vidyut Gopal
IPC分类号： G11C11/00 , G01N27/00 , H01L21/8239
CPC分类号： H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/146 , H01L45/1641
摘要： Methods for producing RRAM resistive switching elements having optimal switching behavior include crystalline phase structural changes. Structural changes indicative of optimal switching behavior include hafnium oxide phases in an interfacial region between a resistive switching layer and an electrode.
摘要翻译：具有最佳切换行为的RRAM电阻式开关元件的制造方法包括晶相结构变化。指示最佳切换行为的结构变化包括在电阻式开关层和电极之间的界面区域中的氧化铪相。

43. 发明申请

US20120313069A1 WORK FUNCTION TAILORING FOR NONVOLATILE MEMORY APPLICATIONS 有权
标题翻译：用于非易失性存储器应用的工作功能定制
公开(公告)号：US20120313069A1
公开(公告)日：2012-12-13
申请号：US13156624
申请日：2011-06-09
申请人： Yun Wang , Tony Chiang , Imran Hashim
发明人： Yun Wang , Tony Chiang , Imran Hashim
IPC分类号： H01L47/00
CPC分类号： H01L45/1608 , H01L27/2463 , H01L45/04 , H01L45/065 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1616 , H01L45/1633 , H01L45/1641
摘要： Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.
摘要翻译：本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。

44. 发明申请

US20100001269A1 Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate 有权
标题翻译：在半导体基板上筛选多个样品的组合处理方法
公开(公告)号：US20100001269A1
公开(公告)日：2010-01-07
申请号：US12167118
申请日：2008-07-02
申请人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
发明人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
IPC分类号： C23C16/00 , H01L21/66 , H01L23/58
CPC分类号： G01R31/2831 , G01R31/2834 , H01L22/34
摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.
摘要翻译：在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

45. 发明申请

US20130056702A1 ATOMIC LAYER DEPOSITION OF METAL OXIDE MATERIALS FOR MEMORY APPLICATIONS 有权
标题翻译：用于存储器应用的金属氧化物材料的原子层沉积
公开(公告)号：US20130056702A1
公开(公告)日：2013-03-07
申请号：US13612000
申请日：2012-09-12
申请人： Yun Wang , Vidyut Gopal , Imran Hashim , Dipankar Pramanik , Tony Chiang
发明人： Yun Wang , Vidyut Gopal , Imran Hashim , Dipankar Pramanik , Tony Chiang
IPC分类号： H01L45/00 , B82Y10/00 , B82Y99/00
CPC分类号： H01L45/145 , C23C16/40 , C23C16/45525 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/022 , H01L21/0228 , H01L27/2463 , H01L45/08 , H01L45/1266 , H01L45/146 , H01L45/1608 , H01L45/1616
摘要： Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.
摘要翻译：本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。设置在金属氧化物层之间的界面有助于氧空位移动。在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对准的晶界，其包含平行于电极界面延伸的许多晶界。因此，氧空缺在切换期间被捕获和释放，而空位明显损失。因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。

46. 发明申请

US20130056700A1 DEFECT GRADIENT TO BOOST NONVOLATILE MEMORY PERFORMANCE 有权
标题翻译：缺陷增强非易失性存储器性能
公开(公告)号：US20130056700A1
公开(公告)日：2013-03-07
申请号：US13223950
申请日：2011-09-01
申请人： Yun Wang , Tony Chiang , Imran Hashim
发明人： Yun Wang , Tony Chiang , Imran Hashim
IPC分类号： H01L45/00
CPC分类号： H01L45/122 , H01L27/2463 , H01L45/08 , H01L45/146 , H01L45/1608
摘要： Embodiments of the present invention generally relate to a resistive switching nonvolatile memory element that is formed in a resistive switching memory device that may be used in a memory array to store digital data. The memory element is generally constructed as a metal-insulator-metal stack. The resistive switching portion of the memory element includes a getter portion and/or a defect portion. In general, the getter portion is an area of the memory element that is used to help form, during the resistive switching memory device's fabrication process, a region of the resistive switching layer that has a greater number of vacancies or defects as compared to the remainder of resistive switching layer. The defect portion is an area of the memory element that has a greater number of vacancies or defects as compared to the remainder of the resistive switching layer, and is formed during the resistive switching memory device's fabrication process. The addition of the getter or defect portions in a formed memory device generally improves the reliability of the resistive switching memory device, improves the switching characteristics of the formed memory device and can eliminate or reduce the need for the time consuming additional post fabrication “burn-in” or pre-programming steps.
摘要翻译：本发明的实施例一般涉及一种电阻式开关非易失性存储元件，其形成在电阻式开关存储器件中，其可用于存储阵列中以存储数字数据。存储元件通常构造为金属 - 绝缘体 - 金属叠层。存储元件的电阻开关部分包括吸气部分和/或缺陷部分。通常，吸气剂部分是存储元件的区域，其用于帮助在电阻式开关存储器件的制造过程期间形成与其余部分相比具有更多数量的空位或缺陷的电阻式开关层的区域的电阻式开关层。缺陷部分是与电阻开关层的其余部分相比具有更多数量的空位或缺陷的存储元件的区域，并且在电阻式开关存储器件的制造过程期间形成。吸收剂或缺陷部分在形成的存储器件中的添加通常提高了电阻式开关存储器件的可靠性，改进了所形成的存储器件的开关特性，并且可以消除或减少对耗时的附加后制造烧坏的需要或预编程步骤。

47. 发明申请

US20130028003A1 NONVOLATILE MEMORY DEVICE HAVING A CURRENT LIMITING ELEMENT 有权
标题翻译：具有电流限制元件的非易失性存储器件
公开(公告)号：US20130028003A1
公开(公告)日：2013-01-31
申请号：US13353000
申请日：2012-01-18
申请人： Yun Wang , Imran Hashim , Tony Chiang
发明人： Yun Wang , Imran Hashim , Tony Chiang
IPC分类号： H01L45/00 , H01L21/8239 , G11C11/21
CPC分类号： H01L45/1253 , G11C13/0007 , G11C13/003 , G11C2213/56 , G11C2213/76 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/148 , H01L45/1616
摘要： Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device.
摘要翻译：本发明的实施例通常包括一种形成非易失性存储器件的方法，该非易失性存储器件包含由于添加限定在其中的限流部件而具有改进的器件切换性能和寿命的电阻式开关存储元件。在一个实施例中，限流部件包括至少一层电阻材料，其被配置为提高所形成的电阻式开关存储元件的开关性能和寿命。形成的限流层或电阻层的电性能被配置为通过在形成的电阻中添加固定的串联电阻来在逻辑状态编程步骤（即，设置和复位步骤）期间降低通过可变电阻层的电流在非易失性存储器件中发现的切换存储器元件。

48. 发明申请

US20120149137A1 Methods of Combinatorial Processing For Screening Multiple Samples on a Semiconductor Substrate 失效
标题翻译：用于在半导体衬底上筛选多个样品的组合处理方法
公开(公告)号：US20120149137A1
公开(公告)日：2012-06-14
申请号：US13399719
申请日：2012-02-17
申请人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
发明人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
IPC分类号： H01L21/66
CPC分类号： G01R31/2831 , G01R31/2834 , H01L22/34
摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.
摘要翻译：在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

49. 发明申请

US20120061799A1 Yttrium and Titanium High-K Dielectric Films 有权
标题翻译：钇和钛高K介电薄膜
公开(公告)号：US20120061799A1
公开(公告)日：2012-03-15
申请号：US12901239
申请日：2010-10-08
申请人： Imran Hashim , Indranil De , Tony Chiang , Edward Haywood , Hanhong Chen , Nobi Fuchigami , Pragati Kumar , Sandra Malhotra , Sunil Shanker
发明人： Imran Hashim , Indranil De , Tony Chiang , Edward Haywood , Hanhong Chen , Nobi Fuchigami , Pragati Kumar , Sandra Malhotra , Sunil Shanker
IPC分类号： H01L29/92
CPC分类号： H01L28/40 , C23C14/083 , C23C14/3464 , C23C16/405 , C23C16/45531 , H01L21/02186 , H01L21/02192 , H01L21/02194 , H01L21/02266 , H01L21/0228
摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.
摘要翻译：本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。如果需要，氧化物层可以通过PVD工艺或者通过使用特定前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺作为反应过程的结果来生产反应。

50. 发明授权

US09390970B2 Method for depositing a diffusion barrier layer and a metal conductive layer 有权
标题翻译：沉积扩散阻挡层和金属导电层的方法
公开(公告)号：US09390970B2
公开(公告)日：2016-07-12
申请号：US11733671
申请日：2007-04-10
申请人： Tony Chiang , Gongda Yao , Peijun Ding , Fusen E. Chen , Barry L. Chin , Gene Y. Kohara , Zheng Xu , Hong Zhang
发明人： Tony Chiang , Gongda Yao , Peijun Ding , Fusen E. Chen , Barry L. Chin , Gene Y. Kohara , Zheng Xu , Hong Zhang
IPC分类号： H01L21/768 , C23C14/04 , C23C14/16 , H01L21/285
CPC分类号： H01L21/76843 , C23C14/046 , C23C14/165 , H01L21/2855 , H01L21/76805 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865 , H01L21/76871 , H01L21/76877 , H01L21/76879 , H01L21/76883
摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.
摘要翻译：我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染。第一保护层的材料通过传统的溅射或离子沉积溅射沉积在衬底表面上，结合足够低的衬底偏压，其中施加了该层的表面在保护层沉积期间不被腐蚀掉或被污染。随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层。

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