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41. 发明授权

US07496870B2 Method of selecting cells in logic restructuring 失效
标题翻译：逻辑重组中选择单元的方法
公开(公告)号：US07496870B2
公开(公告)日：2009-02-24
申请号：US11551573
申请日：2006-10-20
申请人： Iliya V. Lyalin , Andrej A. Zolotykh , Elyar E. Gasanov , Alexei V. Galatenko
发明人： Iliya V. Lyalin , Andrej A. Zolotykh , Elyar E. Gasanov , Alexei V. Galatenko
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.
摘要翻译：本公开涉及一种用于选择用于原始设计的逻辑重组的集成电路中的单元的方法。原始设计包括一组参数。该方法包括形成将包括用于逻辑重组的所选择的单元的重构集合和候选集。重组集合包括具有初始单元格的重组单元。重组集合适于接受被称为重组细胞的额外细胞。候选集合适于包括候选小区，其中候选集合中的每个候选小区连接到重组集合中的至少一个重组小区。候选集合适于从候选集中移除候选细胞。如果在参数集合中包括相应的参数，则重组集合适于接受所选择的被移除的候选小区作为已识别的重组小区。

42. 发明授权

US07003739B2 Method and apparatus for finding optimal unification substitution for formulas in technology library 有权
公开(公告)号：US07003739B2
公开(公告)日：2006-02-21
申请号：US10719787
申请日：2003-11-21
申请人： Elyar E. Gasanov , Alexander S. Podkolzin , Alexei V. Galatenko
发明人： Elyar E. Gasanov , Alexander S. Podkolzin , Alexei V. Galatenko
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present invention is directed to a method and apparatus to find an optimal unification substitution for formulas in a technology library. In an exemplary aspect of the present invention, a method for finding an optimal unification substitution for formulas in a technology library during integrated circuit design may include the following steps: (a) receiving input including a list L of pairs of formulas in standard form, a set S of substitutions for variables, a right part e(x1, . . . , xp) of an identity, and an information I={t, h, r, a, p} on best application; (b) when the list L is not empty, extracting and removing first pair (ƒ′(A′1, . . . , A′n′), g′(B′1, . . . , B′m′)) from the list L; (c) removing head inverters and buffers from formulas ƒ′(A′1, . . . , A′n′) and g′(B′1, . . . , B′m′)) and obtaining a pair (ƒ(A1, . . . , An), g(B1, . . . , Bm)); (d) when the ƒ is a commutative operation but neither a variable nor constant, and when heads of the formulas ƒ(A1, . . . , An) and g(B1, . . . , Bm) are equal, searching for a basic argument Aj of the formula ƒ(A1, . . . , An); (e) when the basic argument Aj is found, letting P be head of said Aj and setting i=1; (f) when head of Bi is equal to the P, making copy L′ of the list L and making copy S′ of the set S; and (g) forming a reduced pair (A′, B′) for pairs (ƒ(A1, . . . , An), ƒ(B1, . . . , Bn)) and (Aj, Bi) and adding the pairs (Aj, Bi) and (A′, B′) to the list L′.

43. 发明授权

US06701503B2 Overlap remover manager 失效
标题翻译：重叠移除管理员
公开(公告)号：US06701503B2
公开(公告)日：2004-03-02
申请号：US10072008
申请日：2002-02-07
申请人： Andrey A. Nikitin , Elyar E. Gasanov , Andrej A. Zolotykh
发明人： Andrey A. Nikitin , Elyar E. Gasanov , Andrej A. Zolotykh
IPC分类号： G06F945
CPC分类号： G06F17/5072
摘要： The present invention is directed to a system and method for providing an overlap remover manager. A method for removing overlaps in a circuit design for an integrated circuit may include initiating an overlap remover manager, wherein the overlap remover manager is suitable for moving cells of an integrated circuit design to remove cell overlaps. A search for critical wires is performed and a determination is made of which violated moves of cells caused at least one critical wire. A determined violated move of the cells is rolled back and the overlap remover manager employed to remove overlaps between rolled back cells.
摘要翻译：本发明涉及一种用于提供重叠去除器管理器的系统和方法。用于去除集成电路的电路设计中的重叠的方法可以包括启动重叠去除器管理器，其中重叠去除器管理器适合于移动集成电路设计的单元以去除单元重叠。执行关键线的搜索，并且确定哪些违反移动的单元造成至少一个关键线。回滚确定的单元格的违反移动，并且使用重叠去除器管理器来去除回滚单元之间的重叠。

44. 发明授权

US06513148B1 Density driven assignment of coordinates 失效
标题翻译：密度驱动分配坐标
公开(公告)号：US06513148B1
公开(公告)日：2003-01-28
申请号：US09844361
申请日：2001-04-27
申请人： Elyar E. Gasanov , Andre J. Zolotykh , Youri P. Postelga
发明人： Elyar E. Gasanov , Andre J. Zolotykh , Youri P. Postelga
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： An optimizing method for integrated circuits wherein coordinates are assigned to cells of a logic tree in a manner that maintains desirable cell density characteristics.
摘要翻译：一种用于集成电路的优化方法，其中以保持期望的单元密度特性的方式将坐标分配给逻辑树的单元。

45. 发明授权

US06470487B1 Parallelization of resynthesis 有权
标题翻译：再合成平行化
公开(公告)号：US06470487B1
公开(公告)日：2002-10-22
申请号：US09842350
申请日：2001-04-25
申请人： Andrej A. Zolotykh , Elyar E. Gasanov , Ivan Pavisic , Aiguo Lu
发明人： Andrej A. Zolotykh , Elyar E. Gasanov , Ivan Pavisic , Aiguo Lu
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A method for resynthesizing a design of an integrated circuit using a parallel processing mode. A single processing mode is entered by activating a main thread and locking a semaphore associated with the main thread. The design of the integrated circuit is resynthesized using the main thread. Tasks to be accomplished in the parallel processing mode are identified. The semaphore associated with the main thread is unlocked, and the operation of the single processing mode is ceased. Ordinal threads are activated by unlocking a semaphore associated with each ordinal thread. The tasks are processed in parallel by assigning the tasks to the ordinal threads and the main thread. Upon completion of one of the assigned tasks by one of the ordinal threads, it is determined whether an additional task remains to be assigned. In the case where the additional task remains, the additional task is assigned to the completed one of the ordinal threads. In the case where the additional task does not remain, the completed one of the ordinal threads is inactivated. Upon inactivation of all of the ordinal threads, a return is made to the single processing mode, with the ordinal threads remaining inactive unless and until the main thread identifies more tasks to be accomplished in the parallel processing mode.
摘要翻译：一种使用并行处理模式重新合成集成电路的设计的方法。通过激活主线程并锁定与主线程相关联的信号量来输入单个处理模式。集成电路的设计使用主线重新合成。识别以并行处理模式完成的任务。与主线程相关联的信号量被解锁，并且停止单处理模式的操作。通过解锁与每个顺序线程相关联的信号量激活有序线程。通过将任务分配给顺序线程和主线程，并行处理任务。在通过其中一个顺序线程完成一个分配的任务之后，确定是否还有一个额外的任务被分配。在附加任务保留的情况下，附加任务被分配给完成的一个序数线程。在附加任务不存在的情况下，完成的一个顺序线程将被禁用。在所有顺序线程失效后，返回到单个处理模式，顺序线程保持不活动，除非主线程在并行处理模式下识别要完成的更多任务。

46. 发明授权

US06175950B1 Method and apparatus for hierarchical global routing descend 失效
标题翻译：分级全局路由下降的方法和装置
公开(公告)号：US06175950B1
公开(公告)日：2001-01-16
申请号：US09062217
申请日：1998-04-17
申请人： Ranko Scepanovic , Alexander E. Andreev , Elyar E. Gasanov , Pedja Raspopovic
发明人： Ranko Scepanovic , Alexander E. Andreev , Elyar E. Gasanov , Pedja Raspopovic
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： Net routing is optimized in an integrated circuit device by dividing an integrated circuit design with a first group of substantially parallel lines in a first direction and with a group of substantially parallel lines in a second direction, with the second direction being substantially perpendicular to the first direction. A first routing graph is formed with vertices corresponding to locations where lines in the first direction and lines in the second direction cross, and nets are globally routed as a function of the first routing graph. The integrated circuit design is further subdivided with a second group of substantially parallel lines in the first direction, and a second routing graph is formed with vertices corresponding to locations where lines in the first and second groups of substantially parallel lines in the first direction cross lines in the group of substantially parallel lines in the second direction. For a net globally routed using the first routing graph, a first local net is formed in a first fragment of the second routing graph, and the first local net is rerouted within the first fragment by computing edge penalty values for edges in the first fragment and rerouting the first local net as a function of the edge penalty values.
摘要翻译：通过将集成电路设计与第一方向上的第一组基本上平行的线分隔开并且在第二方向上与一组基本上平行的线分开，使得第二方向基本上垂直于第一方向方向。第一路由图形成为与第一方向上的线和第二方向上的线交叉的位置相对应的顶点，并且网络作为第一路由图的函数被全局路由。集成电路设计在第一方向上被进一步细分为第二组基本上平行的线，并且第二路由图形成为与第一方向交叉线上的基本上平行的第一组和第二组中的线对应的顶点在第二方向上基本平行的线组。对于使用第一路由图全局路由的网络，在第二路由图的第一片段中形成第一本地网，并且通过计算第一片段中的边缘的边缘惩罚值，在第一片段内重新路由第一本地网，作为边缘惩罚值的函数重新路由第一个本地网络。

47. 发明授权

US07398486B2 Method and apparatus for performing logical transformations for global routing 失效
标题翻译：用于执行全局路由的逻辑转换的方法和装置
公开(公告)号：US07398486B2
公开(公告)日：2008-07-08
申请号：US10803516
申请日：2004-03-17
申请人： Alexei V. Galatenko , Elyar E. Gasanov , Andrej A. Zolotykh
发明人： Alexei V. Galatenko , Elyar E. Gasanov , Andrej A. Zolotykh
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5077
摘要： The present invention provides a new approach and algorithm to optimize various design parameters in global routing. According to an exemplary aspect of the present invention, marked trees are first preprocessed. For every vertex incident to leaves, one may go through the list of its leaves, and if two leaves have the same mark one may leave only one of them. After that whether homeomorphism exists may be determined. The reason behind selecting such homeomorphic pairs is as follows: adding or removing a vertex of degree 2 as well as adding or removing a new leaf (variable) does not significantly modify routing (in this case all routing transformations are in essence splitting and merging routing trees). After the selection of applicable transformations, one may apply them to optimize design parameters. This may be achieved by assigning the same coordinates to nodes of degree !=2 of homeomorphic trees, which means that one may assign the coordinates of corresponding nodes to “essential” nodes and then insert or remove nodes of degree 2.
摘要翻译：本发明提供了一种用于优化全局路由中的各种设计参数的新方法和算法。根据本发明的示例性方面，首先对标记的树进行预处理。对于每个离开的顶点，可以通过它的叶子列表，如果两个叶子有相同的标记，那么可以只留下其中一个。之后，可以确定是否存在同胚。选择这种同胚对之后的原因如下：添加或删除2级顶点以及添加或删除新叶（变量）不会显着修改路由（在这种情况下，所有路由转换本质上都是分割和合并路由树）。选择适用的变换后，可以应用它们来优化设计参数。这可以通过将相同的坐标分配给同胚树的度数= 2的节点来实现，这意味着可以将对应节点的坐标分配给“必需”节点，然后插入或移除度数2的节点。

48. 发明授权

US07103865B2 Process and apparatus for placement of megacells in ICs design 有权
标题翻译：在IC设计中放置大型电池的工艺和设备
公开(公告)号：US07103865B2
公开(公告)日：2006-09-05
申请号：US10719393
申请日：2003-11-21
申请人： Alexei V. Galatenko , Valeriy B. Kudryavtsev , Elyar E. Gasanov
发明人： Alexei V. Galatenko , Valeriy B. Kudryavtsev , Elyar E. Gasanov
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5072
摘要： An IC layout containing megacells placed in violation of design rules is corrected to remove design rule violations while maintaining the original placement as near as practical. The sizes of at least some of the megacells are inflated. The megacells are placed and moved in a footprint of the circuit in a manner to reduce placement complexity. The placement of the megacells is permuted to reduce placement complexity. Additional movements are be applied to the permuted placement to further reduce placement complexity.
摘要翻译：包含违反设计规则的大型电力设备的IC布局被更正，以消除设计规则违规，同时将原始位置保持在可接近的范围内。至少一些大型电池的尺寸是膨胀的。这些巨型电池以一种降低放置复杂性的方式放置并移动到电路的占位面积中。大容量的放置被置换以减少放置复杂性。额外的运动可应用于排列的位置，以进一步降低放置复杂性。

49. 发明授权

US06845495B2 Multidirectional router 失效
标题翻译：多向路由器
公开(公告)号：US06845495B2
公开(公告)日：2005-01-18
申请号：US10027642
申请日：2001-12-20
申请人： Alexandre E. Andreev , Elyar E. Gasanov , Ranko Scepanovic
发明人： Alexandre E. Andreev , Elyar E. Gasanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： The present invention is directed to a system and method for providing multidirectional routing. The present invention may provide an arbitrary number of routing layers and an arbitrary direction on each of those layers to provide a smaller die size and to reduce power consumption by providing more flexibility for net routing directions.
摘要翻译：本发明涉及用于提供多向路由的系统和方法。本发明可以在这些层中的每一层上提供任意数量的路由层和任意方向，以提供更小的管芯尺寸，并通过为网络布线方向提供更多的灵活性来降低功耗。

50. 发明授权

US06701493B2 Floor plan tester for integrated circuit design 失效
标题翻译：集成电路设计平面图测试仪
公开(公告)号：US06701493B2
公开(公告)日：2004-03-02
申请号：US10109113
申请日：2002-03-27
申请人： Elyar E. Gasanov , Andrej A. Zolotykh , Ivan Pavisic , Aiguo Lu
发明人： Elyar E. Gasanov , Andrej A. Zolotykh , Ivan Pavisic , Aiguo Lu
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method of testing a floor plan for an integrated circuit prior to resynthesis includes attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has an unreachable pin; and if the least-penalty path is constructed, then attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has a bottleneck.
摘要翻译：在再合成之前测试集成电路的平面图的方法包括尝试构造在平面图中连接每个长距离销对的销的最小惩罚路径，以确定平面图是否具有不可达的销; 并且如果构造最小惩罚路径，则尝试构建在平面图中连接每个长距离销对的销的最小惩罚路径，以确定平面图是否具有瓶颈。

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