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41. 发明授权

US06998658B2 Twin NAND device structure, array operations and fabrication method 有权
公开(公告)号：US06998658B2
公开(公告)日：2006-02-14
申请号：US10697925
申请日：2003-10-30
申请人： Seiki Ogura , Tomoko Ogura , Tomoya Saito , Kimihiro Satoh
发明人： Seiki Ogura , Tomoko Ogura , Tomoya Saito , Kimihiro Satoh
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： G11C11/5671 , G11C16/0475 , H01L27/115 , H01L27/11568
摘要： A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

42. 发明授权

US06825084B2 Twin NAND device structure, array operations and fabrication method 有权
公开(公告)号：US06825084B2
公开(公告)日：2004-11-30
申请号：US10697520
申请日：2003-10-30
申请人： Seiki Ogura , Tomoko Ogura , Tomoya Saito , Kimihiro Satoh
发明人： Seiki Ogura , Tomoko Ogura , Tomoya Saito , Kimihiro Satoh
IPC分类号： H01L21336
CPC分类号： G11C11/5671 , G11C16/0475 , H01L27/115 , H01L27/11568
摘要： A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

43. 发明授权

US06686632B2 Dual-bit multi-level ballistic MONOS memory 有权
标题翻译：双位多级弹道MONOS内存
公开(公告)号：US06686632B2
公开(公告)日：2004-02-03
申请号：US09839966
申请日：2001-04-23
申请人： Seiki Ogura , Yutaka Hayashi , Tomoko Ogura
发明人： Seiki Ogura , Yutaka Hayashi , Tomoko Ogura
IPC分类号： H01L29792
CPC分类号： H01L27/11568 , G11C11/5671 , G11C16/0475 , H01L27/115
摘要： A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40 nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line. The features of fast program, low voltage, ultra-high density, dual-bit, multi-level MONOS NVRAM of the present invention include: 1) Electron memory storage in nitride regions within an ONO layer underlying the control gates, 2) high density dual-bit cell in which there are two nitride memory storage elements per cell, 3) high density dual-bit cell can store multi-levels in each of the nitride regions, 4) low current program controlled by the word gate and control gate, 5) fast, low voltage program by ballistic injection utilizing the controllable ultra-short channel MONOS, and 6) side wall control poly gates to program and read multi-levels while masking out memory storage state effects of the unselected adjacent nitride regions and memory cells.
摘要翻译：描述了一种快速低电压弹道程序，超短通道，超高密度双位多级闪存。本发明的结构和操作通过具有小于40nm的超短控制栅极通道的双重MONOS单元结构实现，具有提供高电子注入效率的弹道注入和在3〜5V的低编程电压下非常快速的程序。弹道MONOS存储单元被布置在以下阵列中：每个存储单元包含用于一个字门的两个氮化物区域，以及1/2扩散源和1/2位扩散。控制门可以单独定义，也可以通过相同的扩散共享。扩散在单元之间共享并且平行于侧壁控制栅极并垂直于字线。本发明的快速程序，低电压，超高密度，双位多级MONOS NVRAM的特征包括：1）在控制门下面的ONO层内的氮化物区域中的电子存储器存储，2）高密度每个单元有两个氮化物存储器元件的双位单元，3）高密度双位单元可以在每个氮化物区域中存储多个电平; 4）由字门和控制栅极控制的低电流程序， 5）通过使用可控超短通道MONOS的弹道注射的快速，低电压程序，以及6）侧壁控制多门程序来编程和读取多级，同时掩蔽未选择的相邻氮化物区域和存储器单元的存储器存储状态效应。

44. 发明授权

US06459622B1 Twin MONOS memory cell usage for wide program 有权
标题翻译：双MONOS内存单元使用广泛的程序
公开(公告)号：US06459622B1
公开(公告)日：2002-10-01
申请号：US10099030
申请日：2002-03-15
申请人： Seiki Ogura , Tomoko Ogura
发明人： Seiki Ogura , Tomoko Ogura
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C16/10
摘要： The present invention provides a method of memory cell selection and operation to obtain wide program bandwidth and EEPROM erase capability. Two storage sites within a memory cell can be simultaneously selected during read, program and erase. By proper biasing, each of the sites can be independently read and programmed. Also, during program, the source of energy to produce the current flow can be dynamically obtained from the stored charge on the selected bit line. If the bit line capacitance is not adequate to provide a charge that is necessary, additional bit line capacitance is borrowed from unselected bit lines, or a source follower select transistor may be used.
摘要翻译：本发明提供一种存储单元选择和操作的方法，以获得宽的程序带宽和EEPROM擦除能力。可以在读取，编程和擦除期间同时选择存储单元内的两个存储位置。通过适当的偏置，每个站点都可以独立读取和编程。此外，在程序期间，可以从所选位线上的存储电荷动态地获得产生电流的能量源。如果位线电容不足以提供必要的电荷，则附加位线电容从未选择的位线借来，或者可以使用源极跟随器选择晶体管。

45. 发明授权

US06248633B1 Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory 有权
公开(公告)号：US06248633B1
公开(公告)日：2001-06-19
申请号：US09426692
申请日：1999-10-25
申请人： Seiki Ogura , Yutaba Hayashi , Tomoko Ogura
发明人： Seiki Ogura , Yutaba Hayashi , Tomoko Ogura
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , G11C11/5671 , G11C16/0475 , H01L27/115
摘要： A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described with a two or three polysilicon split gate side wall process. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The cell structure is realized by (i) placing side wall control gates over a composite of Oxide-Nitride-Oxide (ONO) on both sides of the word gate, and (ii) forming the control gates and bit diffusion by self-alignment and sharing the control gates and bit diffusions between memory cells for high density. Key elements used in this process are: 1) Disposable side wall process to fabricate the ultra short channel and the side wall control gate with or without a step structure, and 2) Self-aligned definition of the control gate over the storage nitride and the bit line diffusion, which also runs in the same direction as the control gate. The features of fast program, low voltage, ultra-high density, dual-bit, multi-level MONOS NVRAM of the present invention include: 1) Electron memory storage in nitride regions within an ONO layer underlying the control gates, 2) high density dual-bit cell in which there are two nitride memory storage elements per cell, 3) high density dual-bit cell can store multi-levels in each of the nitride regions, 4) low current program controlled by the word gate and control gate, 5) fast, low voltage program by ballistic injection utilizing the controllable ultra-short channel MONOS, and 6) side wall control poly gates to program and read multi-levels while masking out memory storage state effects of the unselected adjacent nitride regions and memory cells. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line.

46. 发明授权

US06177318B1 Integration method for sidewall split gate monos transistor 有权
标题翻译：侧壁分离栅单极晶体管的集成方法
公开(公告)号：US06177318B1
公开(公告)日：2001-01-23
申请号：US09419561
申请日：1999-10-18
申请人： Seiki Ogura , Yutaka Hayashi , Tomoko Ogura
发明人： Seiki Ogura , Yutaka Hayashi , Tomoko Ogura
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/11521
摘要： A fabrication method for an electrically programmable read only memory device, which consists of a control/word gate and a MONOS control gate on the side wall of the control gate. The unique material selection and blocking mask sequences allow simple and safe fabrication within the delicate scaled CMOS process environment, of a sidewall MONOS control gate with an ultra short channel under the control gate, which involves double side wall spacer formation i.e., a disposable side wall spacer and the final polysilicon spacer gate.
摘要翻译：一种用于电可编程只读存储器件的制造方法，其由控制/字门和控制栅极侧壁上的MONOS控制栅极组成。独特的材料选择和阻挡掩模序列允许在精细缩放的CMOS工艺环境内简单和安全地制造具有在控制栅极下方的超短通道的侧壁MONOS控制栅极，其涉及双侧壁间隔物形成，即一次性侧壁间隔物和最终的多晶硅间隔栅极。

47. 发明授权

US07006378B1 Array architecture and operation methods for a nonvolatile memory 有权
标题翻译：非易失性存储器的阵列架构和操作方法
公开(公告)号：US07006378B1
公开(公告)日：2006-02-28
申请号：US10742987
申请日：2003-12-22
申请人： Tomoya Saito , Tomoko Ogura , Kimihiro Satoh , Seiki Ogura
发明人： Tomoya Saito , Tomoko Ogura , Kimihiro Satoh , Seiki Ogura
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： A nonvolatile memory device is achieved. The device comprises a string of MONOS cells connected drain to source. Each MONOS cell comprises a wordline gate overlying a channel region in a substrate. First and second control gates each overlying a channel region in the substrate. The wordline gate channel region is laterally between first and second control gate channel regions. An ONO layer is vertically between the control gates and the substrate. The nitride layer of the ONO layer forms a charge storage site for each control gate. First and second doped regions, forming a source and a drain, are in the substrate. The wordline gate channel region and the control gate channel regions are between the first doped region and the second doped region. First and second transistors connect the topmost MONOS cell to a first bit line and the bottom most MONOS cell to a second bit line.
摘要翻译：实现非易失性存储器件。该装置包括一串连接到源极的MONOS电池。每个MONOS单元包括覆盖衬底中的沟道区的字线门。第一和第二控制栅极，每个覆盖衬底中的沟道区域。字线栅极沟道区域横向在第一和第二控制栅极沟道区域之间。 ONO层在控制栅极和衬底之间垂直。 ONO层的氮化物层形成每个控制栅极的电荷存储位置。在衬底中形成源极和漏极的第一和第二掺杂区域。字线栅极沟道区和控制栅沟道区在第一掺杂区和第二掺杂区之间。第一和第二晶体管将最上面的MONOS单元连接到第一位线，将最底部的MONOS单元连接到第二位线。

48. 发明授权

US06670240B2 Twin NAND device structure, array operations and fabrication method 有权
公开(公告)号：US06670240B2
公开(公告)日：2003-12-30
申请号：US10218210
申请日：2002-08-13
申请人： Seiki Ogura , Tomoko Ogura , Tomoya Saito , Kimihiro Satoh
发明人： Seiki Ogura , Tomoko Ogura , Tomoya Saito , Kimihiro Satoh
IPC分类号： H01L21336
CPC分类号： G11C11/5671 , G11C16/0475 , H01L27/115 , H01L27/11568
摘要： A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

49. 发明授权

US06477088B2 Usage of word voltage assistance in twin MONOS cell during program and erase 有权
标题翻译：在编程和擦除期间，双电极单元中使用字电压辅助
公开(公告)号：US06477088B2
公开(公告)日：2002-11-05
申请号：US10005932
申请日：2001-12-05
申请人： Seiki Ogura , Tomoko Ogura , Tomoya Saito
发明人： Seiki Ogura , Tomoko Ogura , Tomoya Saito
IPC分类号： G11C1604
CPC分类号： G11C16/14 , G11C16/0475
摘要： In the prior arts a twin MONOS memory erase is achieved by applying a positive bias to the bit diffusion and a negative bias to the control gate. The other word gate and substrate terminals are grounded. But the voltage of word gate channel adjacent to the control gate can dramatically influence erase characteristics and speed, due to the short control gate channel length, which is a few times of the carrier escape length. A negative voltage application onto the word gate enhances erase speed, whereas a positive channel potential under the word gate reduces erase speed. By effective biasing of the memory array, word line or even single memory cell level erase is possible without area penalty, as compared to erase blocking by triple well or physical block separations of prior art. Near F-N channel erase without substrate bias application and program disturb protection by word line voltage are also included.
摘要翻译：在现有技术中，通过对位扩散施加正偏压和向控制栅极施加负偏压来实现双MONOS存储器擦除。另一个字栅极和衬底端子接地。但是由于控制栅极通道长度短，是载波逃逸长度的几倍，因此与控制栅极相邻的字门通道的电压可以显着影响擦除特性和速度。字门上的负电压提高了擦除速度，而字门下的正通道电位降低了擦除速度。与现有技术的三阱或物理块分离的擦除阻塞相比，通过存储器阵列的有效偏置，字线或甚至单个存储器单元电平擦除可以没有区域损失。在没有衬底偏置应用的F-N通道擦除附近，还包括通过字线电压的程序干扰保护。

50. 发明授权

US06366500B1 Process for making and programming and operating a dual-bit multi-level ballistic flash memory 有权
公开(公告)号：US06366500B1
公开(公告)日：2002-04-02
申请号：US09656395
申请日：2000-09-06
申请人： Seiki Ogura , Tomoko Ogura
发明人： Seiki Ogura , Tomoko Ogura
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C11/5621 , G11C16/0458 , G11C16/0475 , G11C2211/5612 , H01L27/115 , H01L27/11524
摘要： An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate. In addition to the dual-bit nature of the cell, density can be even further improved by multi-level storage. In one embodiment, the dual multi-level structure is applied to the ballistic step split gate side wall transistor. In a second embodiment, the dual multi-level structure is applied to the ballistic planar split gate side wall transistor. Both types of ballistic transistors provide fast, low voltage programming. The control gates are used to override or suppress the various threshold voltages on associated floating gates, in order to program to and read from individual floating gates. The targets for this non-volatile memory array are to provide the capabilities of high speed, low voltage programming (band width) and high density storage.

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