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41. 发明申请

US20060158930A1 CACT-TG (CATT) low voltage NVM cells 失效
标题翻译： CACT-TG（CATT）低电压NVM电池
公开(公告)号：US20060158930A1
公开(公告)日：2006-07-20
申请号：US11037742
申请日：2005-01-18
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C16/0458 , G11C16/12 , G11C16/14 , H01L27/11556
摘要： Described herein are the methods the CACT and TG Non-volatile program erase methods, for programming and erasing NVM cells. This combination allows use of low voltage methods for program, and erases. The typical cell described uses the “Channel Accelerated Carrier Tunneling (CACT) method for programming memories” for accumulating one type of carriers in the floating gate, and another method, the Tunnel Gun (TG) method, for accumulating the other type of carriers in the floating gate of the cells. These methods use low applied voltages to program and erase the Non-Volatile Memory cell. The proposed CATT (CAcT-Tg) cells by elimination of high voltage requirements are scalable with technology and easily manufacturable using current processes technologies. These cells also have multi-bit storage capability as the program erase methods used are self-limiting in character. Another advantage is the increase in reliability of Cells using this method due to reduced voltage stress.
摘要翻译：这里描述了用于编程和擦除NVM单元的CACT和TG非易失性程序擦除方法。这种组合允许使用低电压方法进行程序和擦除。所描述的典型单元使用“用于编程存储器的通道加速载波隧道（CACT）方法”用于在浮动栅极中累积一种类型的载波，另一种方法是隧道炮（TG）方法，用于将其他类型的载波累加电池的浮动门。这些方法使用低施加电压来编程和擦除非易失性存储单元。通过消除高电压要求，提出的CATT（CAcT-Tg）电池可通过技术进行扩展，并可使用当前工艺技术轻松制造。这些单元还具有多位存储能力，因为使用的程序擦除方法是自限制的。另一个优点是由于降低的电压应力，使用这种方法增加了电池的可靠性。

42. 发明授权

US5989943A Method for fabrication of programmable interconnect structure 失效
公开(公告)号：US5989943A
公开(公告)日：1999-11-23
申请号：US447969
申请日：1989-12-08
申请人： Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas , Hua-Thye Chua , Andrew K. Chan , John M. Birkner
发明人： Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas , Hua-Thye Chua , Andrew K. Chan , John M. Birkner
IPC分类号： H01L21/82 , H01L23/525 , H01L27/10 , H01L21/28
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

43. 发明授权

US4639288A Process for formation of trench in integrated circuit structure using isotropic and anisotropic etching 失效
标题翻译：使用各向同性和各向异性蚀刻在集成电路结构中形成沟槽的工艺
公开(公告)号：US4639288A
公开(公告)日：1987-01-27
申请号：US668225
申请日：1984-11-05
申请人： William L. Price , Ronald L. Schlupp , Mammen Thomas
发明人： William L. Price , Ronald L. Schlupp , Mammen Thomas
IPC分类号： H01L21/76 , H01L21/3065 , H01L21/308 , H01L21/762 , H01L21/763 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/76232 , H01L21/3065 , H01L21/3081 , H01L21/3085 , H01L21/763
摘要： An improved process is disclosed for making an integrated circuit structure wherein a trench is etched into one or more layers to electrically separate one of the devices in the integrated circuit structure from other portions thereof by first patterning silicon dioxide and silicon nitride layer on a layer of silicon. The improvement comprises isotropically etching the silicon layer to provide an enlarged shallow etch area undercutting the patterned silicon dioxide and silicon nitride layers. Subsequent deeper anisotropic etching to form the trench will result in a trench having an enlarged upper width which, in turn, prevents the formation of voids adjacent the upper portion of the trench during subsequent oxidation and polysilicon deposition steps. Possible creation of openings to such voids in the polysilicon during subsequent planarization is thereby eliminated thus avoiding undesirable oxidation of such voids and undesirable stress formation therefrom.
摘要翻译：公开了一种用于制造集成电路结构的改进方法，其中沟槽被蚀刻成一个或多个层，以将集成电路结构中的一个器件与其它部分电气分离，首先在二层二氧化硅和氮化硅层硅。该改进包括各向同性地蚀刻硅层以提供底部图案化的二氧化硅和氮化硅层的扩大的浅蚀刻区域。随后进行更深的各向异性蚀刻以形成沟槽将导致具有扩大的上部宽度的沟槽，这继而在随后的氧化和多晶硅沉积步骤期间防止邻近沟槽上部的空隙的形成。从而消除了在随后的平坦化期间可能在多晶硅中产生这种空隙的开口，从而避免了这种空隙的不期望的氧化和由此产生的不期望的应力。

44. 发明授权

US4616404A Method of making improved lateral polysilicon diode by treating plasma etched sidewalls to remove defects 失效
标题翻译：通过处理等离子体蚀刻侧壁来去除缺陷来制造改进的横向多晶硅二极管的方法
公开(公告)号：US4616404A
公开(公告)日：1986-10-14
申请号：US676684
申请日：1984-11-30
申请人： Scott W. Wang , Mammen Thomas , Wen C. Ko
发明人： Scott W. Wang , Mammen Thomas , Wen C. Ko
IPC分类号： H01L29/78 , H01L21/3215 , H01L21/331 , H01L29/04 , H01L29/73 , H01L29/861 , H01L21/265 , H01L21/425
CPC分类号： H01L29/04 , H01L21/32155 , H01L29/861 , Y10S148/01
摘要： An improved lateral polysilicon diode in an integrated circuit structure is disclosed. The diode is characterized by low reverse current leakage, a breakdown voltage of at least 5 volts, and low series resistance permitting high current flow before being limited by saturation. The polysilicon diode comprises a polysilicon substrate having a first zone sufficiently doped to provide a first semiconductor type and a second zone sufficiently doped to provide a second semiconductor type whereby the junction between the two zones forms a diode. The lateral edges of the diode are treated to remove defects to thereby inhibit current leakage around the edges of the lateral diode to lower the reverse current leakage of the diode.
摘要翻译：公开了一种集成电路结构中的改进的侧向多晶硅二极管。二极管的特征在于低反向电流泄漏，至少5伏的击穿电压，以及在受饱和限制之前允许高电流流动的低串联电阻。多晶硅二极管包括具有充分掺杂以提供第一半导体类型的第一区域和充分掺杂以提供第二半导体类型的第二区域的多晶硅衬底，由此两个区域之间的结形成二极管。对二极管的横向边缘进行处理以消除缺陷，从而抑制横向二极管边缘周围的电流泄漏，以降低二极管的反向电流泄漏。

45. 发明授权

US4468285A Plasma etch process for single-crystal silicon with improved selectivity to silicon dioxide 失效
标题翻译：具有改善二氧化硅选择性的单晶硅的等离子体蚀刻工艺
公开(公告)号：US4468285A
公开(公告)日：1984-08-28
申请号：US564951
申请日：1983-12-22
申请人： Atiye Bayman , Mammen Thomas
发明人： Atiye Bayman , Mammen Thomas
IPC分类号： H01L21/302 , H01L21/205 , H01L21/3065 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/3065
摘要： A plasma etching composition is set forth which comprises chlorine in an amount from about 40% to about 90%, a shape modifier species in an amount from about 10% to about 60%, and an etching selectivity enhancer in an amount sufficient to render the composition at least about 10 times as effective for etching a wafer as for etching a masking layer, the above percents being by mole. The composition is useful for plasma etching of a semiconductor wafer masked with a masking layer having an opening therethrough exposing a portion of the wafer which is to be etched in order to form a depression of a desired depth. This allows depressions of increased depth to be formed in wafers without increasing the thickness of the masking layer.
摘要翻译：提出了一种等离子体蚀刻组合物，其包含约40％至约90％的氯，约10％至约60％的形状改性剂种类和一种蚀刻选择性增强剂，其量足以使组合物对蚀刻掩模层的蚀刻晶片的至少约10倍有效，上述百分比是摩尔数。该组合物对于用具有开口的掩模层掩蔽的半导体晶片的等离子体蚀刻是有用的，暴露待蚀刻的晶片的一部分以形成期望深度的凹陷。这允许在晶片中形成增加深度的凹陷，而不增加掩模层的厚度。

46. 发明授权

US4456501A Process for dislocation-free slot isolations in device fabrication 失效
标题翻译：器件制造中无位错插槽隔离的过程
公开(公告)号：US4456501A
公开(公告)日：1984-06-26
申请号：US564813
申请日：1983-12-22
申请人： Atiye Bayman , Mammen Thomas
发明人： Atiye Bayman , Mammen Thomas
IPC分类号： H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/76 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/3065
摘要： A semiconductor wafer masked with a masking layer having an opening therethrough exposing a portion of the wafer which is to be etched to form a depression of a desired depth is etched via a first plasma etching step under high bias voltage-high energy conditions with a plasma which includes chlorine and a shape modifier species, e.g., argon, to a first depth which is less than the desired depth. Thereafter, the depression is treated by a second plasma etching step under low bias voltage-low energy plasma etching conditions with a plasma which includes chlorine and is substantially free of the shape modifier species. A wet chemical etch follows to remove damaged silicon and impurities. The resulting depression has relatively straight walls and is relatively free of cusps and apexes. The depression is formed quickly and has a desired shape while only a minimal amount of damage and impurities are introduced into the wafer.
摘要翻译：在具有等离子体的高偏压 - 高能条件下经由第一等离子体蚀刻步骤蚀刻半导体晶片，该掩模层具有通过其露出的开口的掩模层，暴露待蚀刻的晶片的一部分以形成所需深度的凹陷，其包括氯和形状调节剂物质，例如氩，至少于所需深度的第一深度。此后，通过第二等离子体蚀刻步骤，在包括氯的等离子体的低偏压 - 低能等离子体蚀刻条件下处理凹陷，并且基本上不含形状修饰物种。遵循湿化学蚀刻去除损坏的硅和杂质。所得到的凹陷具有相对直的壁并且相对没有尖和顶点。凹陷快速形成并且具有期望的形状，同时仅将最少量的损伤和杂质引入晶片。

47. 发明授权

US11956154B2 System for avoiding layer 2 network congestion 有权
公开(公告)号：US11956154B2
公开(公告)日：2024-04-09
申请号：US18201779
申请日：2023-05-25
申请人： George Madathilparambil George , Susan George , Mammen Thomas
发明人： George Madathilparambil George , Susan George , Mammen Thomas
IPC分类号： H04L47/24 , G06F13/40 , G06F13/42 , H04L45/74 , H04L47/125 , H04L49/25 , H04L69/32 , H04L69/324
CPC分类号： H04L47/24 , G06F13/4022 , G06F13/4282 , H04L45/74 , H04L47/125 , H04L49/25 , H04L69/32 , H04L69/324
摘要： Datalink frames or networking packets contain protocol information in the header and optionally in the trailer of a frame or a packet. We are proposing a method in which part of or all of the protocol information corresponding to a frame or a packet is transmitted separately in another datalink frame. The “Separately Transmitted Protocol Information” is referred to as STPI. The STPI contains enough protocol information to identify the next hop node or port. STPI can be used avoid network congestion and improve link efficiency. Preferably, there will be one datalink frame or network packet corresponding to each STPI, containing the data and the rest of the protocol information and this frame/packet is referred to as DFoNP. The creation of STPI and DFoNP is done by the originator of the frame or packet such as an operating system.

48. 发明授权

US11706148B2 Delaying layer 2 frame transmission 有权
公开(公告)号：US11706148B2
公开(公告)日：2023-07-18
申请号：US17834097
申请日：2022-06-07
申请人： George Madathilparambil George , Susan George , Mammen Thomas
发明人： George Madathilparambil George , Susan George , Mammen Thomas
IPC分类号： H04L47/24 , H04L69/32 , H04L69/324 , H04L47/125 , H04L49/25 , G06F13/40 , G06F13/42 , H04L45/74
CPC分类号： H04L47/24 , G06F13/4022 , G06F13/4282 , H04L45/74 , H04L47/125 , H04L49/25 , H04L69/32 , H04L69/324
摘要： Datalink frames or networking packets contain protocol information in the header and optionally in the trailer of a frame or a packet. We are proposing a method in which part of or all of the protocol information corresponding to a frame or a packet is transmitted separately in another datalink frame. The “Separately Transmitted Protocol Information” is referred to as STPI. The STPI contains enough protocol information to identify the next hop node or port. STPI can be used avoid network congestion and improve link efficiency. Preferably, there will be one datalink frame or network packet corresponding to each STPI, containing the data and the rest of the protocol information and this frame/packet is referred to as DFoNP. The creation of STPI and DFoNP is done by the originator of the frame or packet such as an operating system.

49. 发明申请

US20160378708A1 PCI Express to PCI Express based Low Latency Interconnect Scheme for Clustering Systems 审中-公开
标题翻译：用于集群系统的PCI Express到基于PCI Express的低延迟互连方案
公开(公告)号：US20160378708A1
公开(公告)日：2016-12-29
申请号：US15175800
申请日：2016-06-07
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： G06F13/42 , G06F13/40
CPC分类号： G06F13/4282 , G06F13/4022 , G06F13/4221 , G06F2213/0026 , H04L49/40
摘要： PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between multiple PCIE enabled systems each having its own PCIE root complex, such that the scalability of PCIE architecture can be applied to enable data transport between connected systems to form a cluster of systems, is proposed. These connected systems can be any computing, control, storage or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.
摘要翻译： PCI Express是一种总线或I / O互连标准，用于计算机或嵌入式系统内部，可实现更快的数据传输到外围设备。该标准仍在不断发展，但已经达到了一定程度的稳定性，使其他应用程序可以使用PCIE作为基础来实现。一种基于PCIE的互连方案，可实现多个支持PCIE的系统之间的交换和互连，每个PCIE系统都具有自己的PCIE根系，因此PCIE架构的可扩展性可以应用于连接系统之间的数据传输以形成系统集群。提出。这些连接的系统可以是任何计算，控制，存储或嵌入式系统。互连的可扩展性将允许集群在系统变得必要时增加带宽，而不改变到不同的连接体系结构。

50. 发明申请

US20150381501A1 Method for congestion avoidance 审中-公开
标题翻译：避免拥塞的方法
公开(公告)号：US20150381501A1
公开(公告)日：2015-12-31
申请号：US14120845
申请日：2014-07-01
申请人： George Madathilparambil George , Susan George , Mammen Thomas
发明人： George Madathilparambil George , Susan George , Mammen Thomas
IPC分类号： H04L12/851 , H04L12/947 , H04L12/803
CPC分类号： H04L47/24 , G06F13/4022 , G06F13/4282 , H04L45/74 , H04L47/125 , H04L49/25 , H04L69/32 , H04L69/324
摘要： Datalink frames or networking packets contain protocol information in the header and optionally in the trailer of a frame or a packet. We are proposing a method in which part of or all of the protocol information corresponding to a frame or a packet is transmitted separately in another datalink frame. The “Separately Transmitted Protocol Information” is referred to as STPI. The STPI contains enough protocol information to identify the next hop node or port. STPI can be used avoid network congestion and improve link efficiency. Preferably, there will be one datalink frame or network packet corresponding to each STPI, containing the data and the rest of the protocol information and this frame/packet is referred to as DFoNP. The creation of STPI and DFoNP is done by the originator of the frame or packet such as an operating system.
摘要翻译：数据链路帧或网络分组包含报头中的协议信息，并且可选地包含帧或分组的尾部。我们提出了一种方法，其中在另一个数据链路帧中单独传输与帧或分组相对应的协议信息的一部分或全部。 “单独发送的协议信息”被称为STPI。 STPI包含足够的协议信息来标识下一跳节点或端口。 STPI可以避免网络拥塞，提高链路效率。优选地，将存在对应于每个STPI的一个数据链路帧或网络分组，其包含数据和协议信息的其余部分，并且该帧/分组被称为DFoNP。 STPI和DFoNP的创建由帧或数据包的发起者完成，例如操作系统。

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