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41. 发明授权

US07572738B2 Crack stop trenches in multi-layered low-k semiconductor devices 失效
标题翻译：多层低k半导体器件中的裂纹停止沟槽
公开(公告)号：US07572738B2
公开(公告)日：2009-08-11
申请号：US11135313
申请日：2005-05-23
申请人： Takeshi Nogami
发明人： Takeshi Nogami
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76829 , H01L21/76801 , H01L21/76811
摘要： A method is provided for fabricating a semiconductor device. The method begins by forming on a substrate an interconnect stack layer that includes a plurality of layers with interconnecting metal overlying the substrate. After forming the interconnect stack layer, a crack stop trench is formed in the interconnect stack layer. Finally, the crack stop trench is filled with a prescribed material.
摘要翻译：提供了制造半导体器件的方法。该方法开始于在衬底上形成互连堆叠层，所述互连堆叠层包括覆盖衬底的互连金属的多个层。在形成互连叠层之后，在互连叠层中形成裂纹停止沟槽。最后，裂缝停止槽填充规定的材料。

42. 发明申请

US20090127711A1 INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME 审中-公开
标题翻译：互连结构及其制作方法
公开(公告)号：US20090127711A1
公开(公告)日：2009-05-21
申请号：US11940487
申请日：2007-11-15
申请人： Griselda Bonilla , Daniel C. Edelstein , Mahadevaiyer Krishnan , Takeshi Nogami , David L. Rath
发明人： Griselda Bonilla , Daniel C. Edelstein , Mahadevaiyer Krishnan , Takeshi Nogami , David L. Rath
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76847 , H01L21/76805 , H01L21/76883 , H01L23/53238 , H01L2224/13099 , H01L2924/14
摘要： A highly reliable copper interconnect structure and method of fabricating the same is provided. The interconnect structure comprises a metal layer buried between an adjacent upper copper layer and an adjacent lower copper layer structure. More specifically, the interconnect structure comprises a recess formed in a dielectric layer; a barrier metal lining sidewalls of the recess; a first copper layer within the recess; a second copper layer within the recess; and a metal layer buried between the first copper layer and the second copper layer. The method comprises forming a recess in an interlayer dielectric; forming a first copper layer, a metal layer over the first copper layer and a second copper layer over the metal layer, all within the recess. The metal layer is sandwiched between the first copper layer and the second copper layer within the recess.
摘要翻译：提供了一种高度可靠的铜互连结构及其制造方法。互连结构包括埋在相邻的上铜层和相邻的下铜层结构之间的金属层。更具体地，互连结构包括形成在电介质层中的凹部; 衬垫侧壁的阻挡金属衬垫; 凹槽内的第一铜层; 凹槽内的第二铜层; 以及埋在第一铜层和第二铜层之间的金属层。该方法包括在层间电介质中形成凹陷; 在第一铜层上形成第一铜层，金属层和金属层上的第二铜层，全部在凹部内。金属层夹在凹槽内的第一铜层和第二铜层之间。

43. 发明授权

US07422975B2 Composite inter-level dielectric structure for an integrated circuit 失效
标题翻译：用于集成电路的复合层间电介质结构
公开(公告)号：US07422975B2
公开(公告)日：2008-09-09
申请号：US11206361
申请日：2005-08-18
申请人： Takeshi Nogami , Kensaku Ida
发明人： Takeshi Nogami , Kensaku Ida
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/7682
摘要： A method is provided for making an inter-level dielectric for a microelectronic device formed on a substrate. The method begins by forming first and second spacer layers over a substrate layer. The spacer layers are formed from a sacrificial dielectric material. Next, first and second dielectric layers are formed on the first and second spacer layers, respectively, such that each of the first and second dielectric layers is separated by one of the spacer layers. The first and second dielectric layers each include a first and second dielectric component. The second dielectric component is a sacrificial dielectric material. At least a portion of the second dielectric component is removed to thereby form voids in the first and second dielectric layers. At least a portion of the sacrificial dielectric material in the first and second spacer layers is also removed to thereby form voids in the first and/or second spacer layers.
摘要翻译：提供了一种制造用于形成在衬底上的微电子器件的层间电介质的方法。该方法开始于在衬底层上形成第一和第二间隔层。间隔层由牺牲电介质材料形成。接下来，第一和第二电介质层分别形成在第一和第二间隔层上，使得第一和第二电介质层中的每一个被间隔层中的一个隔开。第一和第二介电层各自包括第一和第二介电部件。第二介电部件是牺牲绝缘材料。去除第二电介质部件的至少一部分，从而在第一和第二电介质层中形成空隙。第一和第二间隔层中的牺牲介电材料的至少一部分也被去除，从而在第一和/或第二间隔层中形成空隙。

44. 发明申请

US20070232062A1 Damascene interconnection having porous low k layer followed by a nonporous low k layer 审中-公开
标题翻译：大马士革互连具有多孔低k层，随后是无孔低k层
公开(公告)号：US20070232062A1
公开(公告)日：2007-10-04
申请号：US11395963
申请日：2006-03-31
申请人： Takeshi Nogami
发明人： Takeshi Nogami
IPC分类号： H01L21/4763
CPC分类号： H01L21/76829 , H01L21/76807 , H01L21/76835
摘要： A method is provided for fabricating a damascene interconnection. The method begins by forming on a substrate a porous low k dielectric layer and forming a resist pattern over the low k dielectric layer to define a first interconnect opening. The porous low k dielectric layer is etched through the resist pattern to form the first interconnect opening. The resist pattern is removed and a barrier layer is applied to line the first interconnect opening. An interconnection is formed by filling the first interconnect opening with a conductive material. The interconnection is planarized to remove excess material and a portion of the porous low k dielectric layer damaged by the planarizing step is removed. A nonporous low k dielectric layer is applied after the damaged portion of the porous low k dielectric layer is removed. The interconnection is planarized by removing an excess portion of the nonporous low k dielectric layer.
摘要翻译：提供了用于制造镶嵌互连的方法。该方法开始于在衬底上形成多孔低k电介质层并在低k电介质层上形成抗蚀剂图案以限定第一互连开口。通过抗蚀剂图案蚀刻多孔低k电介质层以形成第一互连开口。去除抗蚀剂图案并且施加阻挡层以使第一互连开口线对齐。通过用导电材料填充第一互连开口形成互连。互连被平坦化以去除多余的材料，并且去除由平坦化步骤损坏的多孔低k电介质层的一部分。在去除多孔低k电介质层的损坏部分之后，施加无孔低k电介质层。通过去除无孔低k电介质层的多余部分来使互连平坦化。

45. 发明申请

US20070231993A1 Damascene interconnection having porous low k layer with a hard mask reduced in thickness 失效
公开(公告)号：US20070231993A1
公开(公告)日：2007-10-04
申请号：US11394011
申请日：2006-03-30
申请人： Masanaga Fukasawa , Takeshi Nogami
发明人： Masanaga Fukasawa , Takeshi Nogami
IPC分类号： H01L21/8238
CPC分类号： H01L21/76829 , H01L21/76807 , H01L21/7684 , H01L21/76849 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method is provided of fabricating a damascene interconnection. The method begins by forming on a substrate a first dielectric layer, a capping layer on the first dielectric sublayer and a resist pattern over the capping layer to define a first interconnect opening. The capping layer and the dielectric layer are etched through the resist pattern to form the first interconnect opening. The resist pattern is removed and a barrier layer is applied over the capping layer and in the first interconnect opening. An interconnection is formed by filling the first interconnect opening with conductive material. The interconnection is planarized to remove excess material and a portion of the first dielectric layer damaged by the planarizing step is selectively etched. A second dielectric layer is applied to replace the damaged portion of the first dielectric.

46. 发明授权

US07202564B2 Advanced low dielectric constant organosilicon plasma chemical vapor deposition films 有权
标题翻译：先进的低介电常数有机硅等离子体化学气相沉积膜
公开(公告)号：US07202564B2
公开(公告)日：2007-04-10
申请号：US10906370
申请日：2005-02-16
申请人： Son Nguyen , Sarah L. Lane , Jia Lee , Kensaku Ida , Darryl D. Restaino , Takeshi Nogami
发明人： Son Nguyen , Sarah L. Lane , Jia Lee , Kensaku Ida , Darryl D. Restaino , Takeshi Nogami
IPC分类号： H01L23/48
CPC分类号： H01L21/7682 , C23C16/401 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02354 , H01L21/3122 , H01L21/31633 , H01L2221/1047
摘要： A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.
摘要翻译：在介电常数小于约3.0的共价键合的三维网络结构中，包含Si，C，O和H原子（以下称为“SiCOH”）的多孔低k或超低k电介质膜，结晶度更高键合相互作用，提供比现有技术的SiCOH电介质更多的碳作为甲基端基和较少的亚甲基-CH 2 - 2交联基团。 SiCOH电介质的特征在于具有小于约1.40的CH 3/3 CH 2拉伸的峰面积的FTIR光谱，SiH拉伸的峰面积小于约0.20，SiCH 3键的峰面积大于约2.0，Si-O-Si键合的峰面积大于约60％，孔隙率大于约20％。

47. 发明申请

US20070051638A1 Electropolishing liquid, electropolishing method, and method for fabricating semiconductor device 审中-公开
标题翻译：电抛光液，电解抛光方法及制造半导体器件的方法
公开(公告)号：US20070051638A1
公开(公告)日：2007-03-08
申请号：US11591688
申请日：2006-11-01
申请人： Shuzo Sato , Takeshi Nogami , Shingo Takahashi , Naoki Komai , Kaori Tai , Hiroshi Horikoshi , Hiizu Ohtorii
发明人： Shuzo Sato , Takeshi Nogami , Shingo Takahashi , Naoki Komai , Kaori Tai , Hiroshi Horikoshi , Hiizu Ohtorii
IPC分类号： B23H5/00
CPC分类号： C09G1/02 , C25F3/02 , C25F3/16 , H01L21/32125
摘要： Electric conductivity is enhanced without causing coagulation or precipitation of polishing abrasive grains. In addition, good planarization is realized without inducing defects in a metallic film or a wiring which are to be polished. In an electropolishing method for planarizing the surface of a metallic film to be polished by moving a polishing pad (15) in sliding contact with the metallic film surface while oxidizing the metallic film surface through an electrolytic action in an electropolishing liquid E, the electropolishing liquid E contains at least polishing abrasive grains and an electrolyte for maintaining an electrostatically charged state of the polishing abrasive grains. Since the electropolishing liquid having a high electric conductivity is used, it is possible to obtain a high electrolyzing current and to enlarge the distance between electrodes. Besides, in the electropolishing method, the electropolishing liquid with a good dispersion state of the polishing abrasive grains is used, so that remaining of the abrasive grains and defects such as scratches are prevented from being generated upon polishing.
摘要翻译：电导率提高而不引起研磨磨粒的凝结或沉淀。此外，实现良好的平坦化，而不会引起要抛光的金属膜或布线的缺陷。在电抛光方法中，通过在电解抛光液体E中通过电解作用使金属膜表面氧化而移动与金属膜表面滑动接触的抛光垫（15）来平坦化待抛光的金属膜的表面，电抛光液 E至少含有抛光磨粒和用于保持抛光磨粒的静电充电状态的电解质。由于使用具有高导电性的电解抛光液体，因此可以获得高的电解电流并且扩大电极之间的距离。此外，在电抛光方法中，使用具有抛光磨粒的良好分散状态的电解抛光液，从而防止在研磨时残留磨粒和划痕等缺陷。

48. 发明授权

US07156975B2 Polishing method and electropolishing apparatus 有权
标题翻译：抛光方法和电抛光装置
公开(公告)号：US07156975B2
公开(公告)日：2007-01-02
申请号：US10304174
申请日：2002-11-26
申请人： Shuzo Sato , Takeshi Nogami , Zenya Yasuda , Masao Ishihara
发明人： Shuzo Sato , Takeshi Nogami , Zenya Yasuda , Masao Ishihara
IPC分类号： C25F3/16 , C25F7/00 , B23H5/06 , B23H3/02 , C25F3/22
CPC分类号： B24B37/013 , B24B49/04 , B24B49/10
摘要： A polishing method for electropolishing a metal film formed on a wafer surface so as to fill concave portions formed on the wafer surface comprises a step of determining an electropolishing end point of the metal film on the basis of a change of a current waveform resulting from electropolishing the metal film. An electropolishing apparatus comprising a current detector for detecting a current waveform resulting from electropolishing a metal film and an end point determination part for determining an electropolishing end point of the metal film on the basis of the change of a current detected with the current detector is used to realize the polishing method.
摘要翻译：电抛光形成在晶片表面上以形成在晶片表面上的凹部的金属膜的抛光方法包括基于电抛光产生的电流波形的变化来确定金属膜的电抛光终点的步骤金属膜。使用电抛光装置，其包括用于检测由电解抛光金属膜产生的电流波形的电流检测器和用于基于由电流检测器检测的电流变化来确定金属膜的电抛光终点的终点确定部件实现抛光方法。

49. 发明申请

US20060183345A1 ADVANCED LOW DIELECTRIC CONSTANT ORGANOSILICON PLASMA CHEMICAL VAPOR DEPOSITION FILMS 有权
标题翻译：高级低介电常数有机硅等离子体化学气相沉积膜
公开(公告)号：US20060183345A1
公开(公告)日：2006-08-17
申请号：US10906370
申请日：2005-02-16
申请人： Son Nguyen , Sarah Lane , Jia Lee , Kensaku Ida , Darryl Restaino , Takeshi Nogami
发明人： Son Nguyen , Sarah Lane , Jia Lee , Kensaku Ida , Darryl Restaino , Takeshi Nogami
IPC分类号： H01L21/31
CPC分类号： H01L21/7682 , C23C16/401 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02354 , H01L21/3122 , H01L21/31633 , H01L2221/1047
摘要： A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.
摘要翻译：在介电常数小于约3.0的共价键合的三维网络结构中，包含Si，C，O和H原子（以下称为“SiCOH”）的多孔低k或超低k电介质膜，结晶度更高键合相互作用，提供比现有技术的SiCOH电介质更多的碳作为甲基端基和较少的亚甲基-CH 2 - 2交联基团。 SiCOH电介质的特征在于具有包含小于约1.40的CH 3 N 2 CH 2拉伸的峰面积的FTIR光谱，SiH拉伸的峰面积小于约0.20，SiCH 3键的峰面积大于约2.0，Si-O-Si键合的峰面积大于约60％，孔隙率大于约20％。

50. 发明申请

US20050224368A1 Polishing system and polishing method 审中-公开
标题翻译：抛光系统和抛光方法
公开(公告)号：US20050224368A1
公开(公告)日：2005-10-13
申请号：US10512185
申请日：2003-04-14
申请人： Shuzo Sato , Takeshi Nogami , Shingo Takahashi , Naoki Komai , Kaori Tai , Hiroshi Horikoshi , Hiizu Ohtorii
发明人： Shuzo Sato , Takeshi Nogami , Shingo Takahashi , Naoki Komai , Kaori Tai , Hiroshi Horikoshi , Hiizu Ohtorii
IPC分类号： B23H5/06 , B24B53/00 , B24B53/007 , C25F3/16 , H01L21/321 , B23H5/02
CPC分类号： B24B53/017 , B24B53/001 , C25F3/16 , H01L21/32125
摘要： A polishing apparatus and a polishing method by which it is possible to restrain variations in the composition of an electrolytic solution 2 between a wafer 3 and a counter electrode 5, and the like, and to make current density distribution substantially constant in the plane of the wafer. The polishing apparatus, for planarizing a surface to be polished 3a by electrolytic combined polishing composed of a combination of electropolishing and mechanical polishing, includes a voltage impressing means 5 disposed oppositely to the surface to be polished 3a, and a discharging means for discharging foreign matter intermediately present between the voltage impressing means 5 and the object of polishing.
摘要翻译：可以抑制晶片3和对电极5之间的电解液2的组成变化等的抛光装置和抛光方法，并使电流密度分布在晶圆。用于通过电抛光和机械抛光组合的电解组合抛光来平坦化待抛光表面3a的抛光装置包括与待抛光表面3a相对设置的电压施加装置5，以及用于放电的放电装置电压施加装置5和抛光对象之间中间存在异物。

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