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41. 发明授权

US08530980B2 Gate stack structure with etch stop layer and manufacturing process thereof 有权
标题翻译：具有蚀刻停止层的栅极叠层结构及其制造工艺
公开(公告)号：US08530980B2
公开(公告)日：2013-09-10
申请号：US13094953
申请日：2011-04-27
申请人： Kun-Hsien Lin , Hsin-Fu Huang , Chi-Mao Hsu , Chin-Fu Lin , Chun-Yuan Wu
发明人： Kun-Hsien Lin , Hsin-Fu Huang , Chi-Mao Hsu , Chin-Fu Lin , Chun-Yuan Wu
IPC分类号： H01L29/78
CPC分类号： H01L21/31144 , H01L21/28008 , H01L29/401 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： A gate stack structure with an etch stop layer is provided. The gate stack structure is formed over a substrate. A spacer is formed on a sidewall of the gate stack structure. The gate stack structure includes a gate dielectric layer, a barrier layer, a repair layer and the etch stop layer. The gate dielectric layer is formed on the substrate. The barrier layer is formed on the gate dielectric layer. The barrier layer and an inner sidewall of the spacer collectively define a trench. The repair layer is formed on the barrier layer and an inner wall of the trench. The etch stop layer is formed on the repair layer.
摘要翻译：提供具有蚀刻停止层的栅极堆叠结构。栅极堆叠结构形成在衬底上。在栅堆叠结构的侧壁上形成间隔物。栅极堆叠结构包括栅极介电层，阻挡层，修复层和蚀刻停止层。栅极电介质层形成在基板上。阻挡层形成在栅介质层上。隔离层和间隔物的内侧壁共同限定沟槽。修复层形成在阻挡层和沟槽的内壁上。蚀刻停止层形成在修复层上。

42. 发明申请

US20130113053A1 SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 有权
标题翻译：半导体结构及其工艺
公开(公告)号：US20130113053A1
公开(公告)日：2013-05-09
申请号：US13288041
申请日：2011-11-03
申请人： Kun-Hsien Lin , Chun-Hsien Lin , Hsin-Fu Huang
发明人： Kun-Hsien Lin , Chun-Hsien Lin , Hsin-Fu Huang
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/265 , H01L21/28088 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure includes a substrate, a dielectric layer and a fluoride metal layer. The dielectric layer is located on the substrate. The fluoride metal layer is located on the dielectric layer. Furthermore, the present invention also provides a semiconductor process to form said semiconductor structure.
摘要翻译：半导体结构包括基板，电介质层和氟化金属层。电介质层位于衬底上。氟化金属层位于电介质层上。此外，本发明还提供了形成所述半导体结构的半导体工艺。

43. 发明授权

US08431999B2 Low capacitance transient voltage suppressor 有权
标题翻译：低电容瞬态电压抑制器
公开(公告)号：US08431999B2
公开(公告)日：2013-04-30
申请号：US13072138
申请日：2011-03-25
申请人： Yu-Shu Shen , Kun-Hsien Lin , Che-Hao Chuang , Ryan Hsin-Chin Jiang
发明人： Yu-Shu Shen , Kun-Hsien Lin , Che-Hao Chuang , Ryan Hsin-Chin Jiang
IPC分类号： H01L23/62 , H01L21/336
CPC分类号： H01L27/0255 , H01L29/861
摘要： A low capacitance transient voltage suppressor is disclosed. The suppressor comprises an N-type heavily doped substrate and an epitaxial layer formed on the substrate. At least one steering diode structure formed in the epitaxial layer comprises a diode lightly doped well and a first P-type lightly doped well, wherein a P-type heavily doped area is formed in the diode lightly doped well and a first N-type heavily doped area and a second P-type heavily doped area are formed in the first P-type lightly doped well. A second P-type lightly doped well having two N-type heavily doped areas is formed in the epitaxial layer. In addition, an N-type heavily doped well and at least one deep isolation trench are formed in the epitaxial layer, wherein the trench has a depth greater than or equal to depths of all the doped wells, so as to separate at least one doped well.
摘要翻译：公开了一种低电容瞬态电压抑制器。抑制器包括N型重掺杂衬底和形成在衬底上的外延层。形成在外延层中的至少一个转向二极管结构包括二极管轻掺杂阱和第一P型轻掺杂阱，其中在二极管轻掺杂阱中形成P型重掺杂区，并且第一N型重掺杂阱在第一P型轻掺杂阱中形成掺杂区域和第二P型重掺杂区域。在外延层中形成具有两个N型重掺杂区的第二P型轻掺杂阱。此外，在外延层中形成N型重掺杂阱和至少一个深隔离沟槽，其中沟槽的深度大于或等于所有掺杂阱的深度，以便分离至少一个掺杂的好。

44. 发明申请

US20120322218A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120322218A1
公开(公告)日：2012-12-20
申请号：US13161591
申请日：2011-06-16
申请人： Chien-Ming LAI , Yi-Wen Chen , Zhi-Cheng Lee , Tong-Jyun Huang , Che-Hua Hsu , Kun-Hsien Lin , Tzung-Ying Lee , Chi-Mao Hsu , Hsin-Fu Huang , Chin-Fu Lin
发明人： Chien-Ming LAI , Yi-Wen Chen , Zhi-Cheng Lee , Tong-Jyun Huang , Che-Hua Hsu , Kun-Hsien Lin , Tzung-Ying Lee , Chi-Mao Hsu , Hsin-Fu Huang , Chin-Fu Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/28088 , H01L21/32134 , H01L21/823842 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7833
摘要： A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.
摘要翻译：一种制造半导体器件的方法包括以下步骤。首先，提供具有伪栅极电极层的虚拟栅极结构。然后，去除虚拟栅极电极层，以在虚拟栅极结构中形成开口，从而暴露在伪栅极电极层下面的下面的层。然后，进行氢氧化铵处理处理以处理伪栅极结构。之后，将金属材料填充到开口中。

45. 发明授权

US08237193B2 Lateral transient voltage suppressor for low-voltage applications 有权
标题翻译：用于低压应用的侧向瞬态电压抑制器
公开(公告)号：US08237193B2
公开(公告)日：2012-08-07
申请号：US12837128
申请日：2010-07-15
申请人： Che-Hao Chuang , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
发明人： Che-Hao Chuang , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
IPC分类号： H01L29/06
CPC分类号： H01L27/0255
摘要： A lateral transient voltage suppressor for low-voltage applications. The suppressor includes an N-type heavily doped substrate and at least two clamp diode structures horizontally arranged in the N-type heavily doped substrate. Each clamp diode structure further includes a clamp well arranged in the N-type heavily doped substrate and having a first heavily doped area and a second heavily doped area. The first and second heavily doped areas respectively belong to opposite conductivity types. There is a plurality of deep isolation trenches arranged in the N-type heavily doped substrate and having a depth greater than depth of the clamp well. The deep isolation trenches can separate each clamp well. The present invention avoids the huge leakage current to be suitable for low-voltage application.
摘要翻译：用于低电压应用的横向瞬态电压抑制器。抑制器包括N型重掺杂衬底和水平地布置在N型重掺杂衬底中的至少两个钳位二极管结构。每个钳位二极管结构还包括在N型重掺杂衬底中布置的具有第一重掺杂区域和第二重掺杂区域的钳位阱。第一和第二重掺杂区域分别属于相反的导电类型。在N型重掺杂衬底中布置有多个深的隔离沟槽，其深度大于夹具阱的深度。深的隔离沟槽可以很好地分离每个夹具。本发明避免了巨大的漏电流适合于低电压应用。

46. 发明授权

US08217462B2 Transient voltage suppressors 有权
公开(公告)号：US08217462B2
公开(公告)日：2012-07-10
申请号：US12888151
申请日：2010-09-22
申请人： Kun-Hsien Lin , Che-Hao Chuang , Ryan Hsin-Chin Jiang
发明人： Kun-Hsien Lin , Che-Hao Chuang , Ryan Hsin-Chin Jiang
IPC分类号： H01L23/62
CPC分类号： H01L29/8613 , H01L27/0255 , H01L27/0259 , H01L29/866
摘要： The present invention relates a transient voltage suppressor (TVS) for directional ESD protection. The TVS includes: a conductivity type substrate; a first type lightly doped region, having a first type heavily doped region arranged therein; a second type lightly doped region, having a second type heavily doped region and a third type heavily doped region arranged therein; a third type lightly doped region, having a fourth type heavily doped region arranged therein; a plurality of closed isolation trenches, arranged on the conductivity type substrate, wherein at least one of the plurality of closed isolation trenches is neighbored one of the type lightly doped regions; and a first pin. Accordingly, the TVS of present invention may adaptively provide effective ESD protection under positive and negative ESD stresses, improve the efficiency of ESD protection within the limited layout area.

47. 发明申请

US20090315803A1 ANTENNA RADOME 有权
标题翻译：天线射线
公开(公告)号：US20090315803A1
公开(公告)日：2009-12-24
申请号：US12335585
申请日：2008-12-16
申请人： Chun-Yih Wu , Hung-Hsuan Lin , Ken-Huang Lin , Kun-Hsien Lin , Yu-Feng Yeh
发明人： Chun-Yih Wu , Hung-Hsuan Lin , Ken-Huang Lin , Kun-Hsien Lin , Yu-Feng Yeh
IPC分类号： H01Q1/42 , H01Q1/38
CPC分类号： H01Q1/42 , H01Q1/422 , H01Q9/0407 , H01Q19/06
摘要： An antenna radome is provided. The antenna radome comprises an antenna radome substrate and a unit cell. The unit cell is formed on a surface of the antenna radome substrate, and the unit cell is perpendicular to a magnetic field direction of an antenna.
摘要翻译：提供天线雷达罩。天线天线罩包括天线天线罩基板和单元电池。单位电池形成在天线罩天线罩基板的表面上，并且单位电池垂直于天线的磁场方向。

48. 发明申请

US20060110917A1 Method of metallization in the fabrication of integrated circuit devices 审中-公开
标题翻译：集成电路器件制造中的金属化方法
公开(公告)号：US20060110917A1
公开(公告)日：2006-05-25
申请号：US11163055
申请日：2005-10-03
申请人： Shu-Jen Chen , Chia-Lin Hsu , Kun-Hsien Lin
发明人： Shu-Jen Chen , Chia-Lin Hsu , Kun-Hsien Lin
IPC分类号： H01L21/44
CPC分类号： H01L21/7684 , H01L21/76877
摘要： The method of metallization in the fabrication of an integrated circuit device comprises the steps as follows. First, a dielectric layer overlying a semiconductor substrate is provided. The dielectric layer has a top surface and a plurality of openings. Next, a metal layer is formed on the dielectric layer and filling the openings. Subsequently, a first removing process is performed to partially removing the metal layer. A first annealing process is performed on the metal layer. Finally, a second removing process is performed to remove the metal layer completely to leave the metal layer only within the openings.
摘要翻译：集成电路器件制造中的金属化方法包括以下步骤。首先，提供覆盖在半导体衬底上的电介质层。电介质层具有顶表面和多个开口。接下来，在电介质层上形成金属层并填充开口。随后，执行第一去除处理以部分地去除金属层。在金属层上进行第一退火处理。最后，进行第二次去除处理，以完全去除金属层，仅将金属层留在开口内。

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