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41. 发明申请

US20090108673A1 METHOD FOR DETERMINING A VOLTAGE LEVEL ACROSS AN ELECTRIC CIRCUIT OF A POWERTRAIN 有权
标题翻译：用于确定动力系统的电路中的电压电平的方法
公开(公告)号：US20090108673A1
公开(公告)日：2009-04-30
申请号：US12253214
申请日：2008-10-16
申请人： Wei D. Wang , William R. Cawthorne , Aniket Kothari , Nicolas Kokotovich , Wei Ren , Bo Zhang
发明人： Wei D. Wang , William R. Cawthorne , Aniket Kothari , Nicolas Kokotovich , Wei Ren , Bo Zhang
IPC分类号： G01R19/00 , B60L1/00
CPC分类号： B60W20/00 , B60K1/02 , B60K6/365 , B60K6/445 , B60K6/547 , B60L3/0046 , B60L11/123 , B60L11/14 , B60L11/1851 , B60L11/187 , B60L2240/423 , B60L2240/441 , B60L2240/443 , B60L2240/445 , B60L2240/461 , B60L2240/465 , B60L2240/486 , B60L2240/662 , B60W10/02 , B60W10/06 , B60W10/08 , B60W2510/0638 , B60W2510/0657 , B60W2510/0671 , B60W2510/0676 , B60W2510/1015 , B60W2510/104 , B60W2510/244 , B60W2510/246 , B60W2520/28 , B60W2540/10 , B60W2540/12 , B60W2540/16 , B60W2550/12 , B60W2710/027 , B60W2710/0605 , B60W2710/0616 , B60W2710/0666 , B60W2710/083 , Y02T10/6217 , Y02T10/6239 , Y02T10/6286 , Y02T10/642 , Y02T10/7005 , Y02T10/705 , Y02T10/7077 , Y02T10/7291 , Y02T90/16
摘要： A method for determining a voltage level across an electrical circuit of a powertrain includes measuring a plurality of voltage levels and utilizing a comparison test between at least two voltage levels of the plurality of voltage levels to determine the circuit voltage level.
摘要翻译：用于确定跨越动力系的电路的电压电平的方法包括测量多个电压电平并且利用多个电压电平的至少两个电压电平之间的比较测试来确定电路电压电平。

42. 外观设计

USD582633S1 Pocket 有权
标题翻译：口袋
公开(公告)号：USD582633S1
公开(公告)日：2008-12-16
申请号：US29308554
申请日：2008-06-20
申请人： Bo Zhang
设计人： Bo Zhang

43. 发明申请

US20080121534A1 NANOPORE ELECTRODE, NANOPORE MEMBRANE, METHODS OF PREPARATION AND SURFACE MODIFICATION, AND USE THEREOF 有权
标题翻译： NANOPORE ELECTRODE，NANOPORE MEMBRANE，METHODS OF PROBARATION AND SURFACE MODIFICATION，AND USE THEREOF
公开(公告)号：US20080121534A1
公开(公告)日：2008-05-29
申请号：US11744154
申请日：2007-05-03
申请人： Henry S. White , Bo Zhang , Ryan J. White , Eric N. Ervin , Gangli Wang
发明人： Henry S. White , Bo Zhang , Ryan J. White , Eric N. Ervin , Gangli Wang
IPC分类号： G01N27/26 , B32B38/10 , C23F1/00
CPC分类号： B01D71/04 , B01D67/006 , B01D2325/021 , Y10S977/904 , Y10S977/953 , Y10T29/49 , Y10T29/49002 , Y10T29/49004 , Y10T29/49826
摘要： Provided are fabrication, characterization and application of a nanodisk electrode, a nanopore electrode and a nanopore membrane. These three nanostructures share common fabrication steps. In one embodiment, the fabrication of a disk electrode involves sealing a sharpened internal signal transduction element (“ISTE”) into a substrate, followed by polishing of the substrate until a nanometer-sized disk of the ISTE is exposed. The fabrication of a nanopore electrode is accomplished by etching the nanodisk electrode to create a pore in the substrate, with the remaining ISTE comprising the pore base. Complete removal of the ISTE yields a nanopore membrane, in which a conical shaped pore is embedded in a thin membrane of the substrate.
摘要翻译：提供了纳米棒电极，纳米孔电极和纳米孔膜的制造，表征和应用。这三种纳米结构具有共同的制造步骤。在一个实施例中，盘形电极的制造包括将锐化的内部信号转导元件（“ISTE”）密封到衬底中，随后抛光衬底直至暴露出ISTE的纳米尺寸的盘。纳米孔电极的制造通过蚀刻纳米盘电极以在衬底中产生孔而实现，剩余的ISTE包含孔基。完全去除ISTE产生纳米孔膜，其中锥形孔被嵌入在基底的薄膜中。

44. 发明申请

US20070075397A1 On-chip capacitor structure 有权
标题翻译：片上电容器结构
公开(公告)号：US20070075397A1
公开(公告)日：2007-04-05
申请号：US11241142
申请日：2005-09-30
申请人： Bo Zhang
发明人： Bo Zhang
IPC分类号： H01L29/00
CPC分类号： H01L28/40 , H01L23/5223 , H01L27/0805 , H01L28/87 , H01L28/91 , H01L29/93 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： A first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and a second capacitor is formed on the substrate and connected to a second differential node of the differential circuit. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate.
摘要翻译：第一电容器形成在衬底上并连接到差分电路的第一差分节点，并且第二电容器形成在衬底上并连接到差分电路的第二差分节点。第三电容器连接在第一差分节点和第二差分节点之间，并且至少部分地形成在第一电容器的上方。以这种方式，可以在基板上减小第一电容器和/或第二电容器的尺寸。

45. 发明申请

US20060222251A1 Method and system for frame/field coding 审中-公开
标题翻译：帧/场编码的方法和系统
公开(公告)号：US20060222251A1
公开(公告)日：2006-10-05
申请号：US11096468
申请日：2005-04-01
申请人： Bo Zhang
发明人： Bo Zhang
IPC分类号： G06K9/36
CPC分类号： H04N19/533 , H04N19/112 , H04N19/16
摘要： Described herein is a system and method for encoding video data with motion estimation. The system and method can optimize memory usage and enhance the perceptual quality of an encoded picture by combining the processes in adaptive frame/field coding.
摘要翻译：这里描述了一种用于利用运动估计对视频数据进行编码的系统和方法。该系统和方法可以通过组合自适应帧/场编码中的处理来优化存储器使用并增强编码图像的感知质量。

46. 发明申请

US20060222063A1 Method and system for rate control in a video encoder 失效
标题翻译：视频编码器速率控制方法及系统
公开(公告)号：US20060222063A1
公开(公告)日：2006-10-05
申请号：US11096467
申请日：2005-04-01
申请人： Bo Zhang , Reinhard Schumann
发明人： Bo Zhang , Reinhard Schumann
IPC分类号： H04N11/04 , H04N7/12 , H04B1/66 , H04N11/02
CPC分类号： H04N19/53 , H04N19/102 , H04N19/103 , H04N19/124 , H04N19/146 , H04N19/172 , H04N19/176 , H04N19/177 , H04N19/56 , H04N19/91
摘要： Described herein is a rate controller in a video system. The rate controller estimates a bit count, and controls three adaptive rate control loops. The master rate control loop is in control of the quantizer. The slave rate control loops control coarse motion estimation and fine motion estimation.
摘要翻译：这里描述的是视频系统中的速率控制器。速率控制器估计位计数，并控制三个自适应速率控制回路。主速率控制回路控制量化器。从速率控制循环控制粗略运动估计和精细运动估计。

47. 发明申请

US20060002497A1 PHASE ADJUSTMENT METHOD AND CIRCUIT FOR DLL-BASED SERIAL DATA LINK TRANSCEIVERS 失效
标题翻译：基于DLL的串行数据链路收发器的相位调整方法和电路
公开(公告)号：US20060002497A1
公开(公告)日：2006-01-05
申请号：US10882428
申请日：2004-07-02
申请人： Bo Zhang
发明人： Bo Zhang
IPC分类号： H04B17/00 , H03D1/00 , H04L27/06 , H04L7/00
CPC分类号： H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/033 , H04L7/0337 , H04L27/06
摘要： A delay locked loop circuit with a first flip flop driven by a 0° clock and receiving the input data. A second flip flop by a 180° clock and receiving the input data. A first demultiplexer receives an output of the first flip flop and outputs peak data. A second demultiplexer receives an output of the second flip flop and outputs zero data. A timing recovery circuit outputs phase control bits based on the zero data and the peak data. A first phase interpolator outputs the 0° clock based on the phase control signal. A second phase interpolator outputs the 180° clock based on the phase control signal. A phase register receives the phase control signal from the timing recovery circuit. The first and second flip flops can be D flip flops. The first and second phase interpolators adjust relative phases of the 0° clock and 180° clock based on the phase control signal. The phase control signal can be a digital signal comprising a plurality of bits corresponding to a phase relationship between the 0° clock and 180° clock. The timing recovery circuit can be a digital circuit. The phase control signal is used to maintain a transition of the 0° clock near a center of an “eye” in the input data.
摘要翻译：一个延迟锁定环电路，具有由0°时钟驱动并接收输入数据的第一触发器。一个180°时钟的第二个触发器，并接收输入数据。第一解复用器接收第一触发器的输出并输出峰值数据。第二解复用器接收第二触发器的输出并输出零数据。定时恢复电路根据零数据和峰值数据输出相位控制位。第一相位内插器基于相位控制信号输出0°时钟。第二相位内插器根据相位控制信号输出180°时钟。相位寄存器从定时恢复电路接收相位控制信号。第一和第二触发器可以是D触发器。第一和第二相位内插器根据相位控制信号调节0°时钟和180°时钟的相对相位。相位控制信号可以是包括对应于0°时钟和180°时钟之间的相位关系的多个位的数字信号。定时恢复电路可以是数字电路。相位控制信号用于保持输入数据中靠近“眼睛”中心的0°时钟的转变。

48. 发明申请

US20050259652A1 Method for forwarding multimedia messages between multimedia messaging service centers 审中-公开
标题翻译：在多媒体消息服务中心之间转发多媒体消息的方法
公开(公告)号：US20050259652A1
公开(公告)日：2005-11-24
申请号：US11127760
申请日：2005-05-11
申请人： Fei Tang , Xiaobin Li , Minghai Liu , Bo Zhang , Yong Meng , Weishu Yang
发明人： Fei Tang , Xiaobin Li , Minghai Liu , Bo Zhang , Yong Meng , Weishu Yang
IPC分类号： H04W4/24 , H04B7/26 , H04L12/14 , H04L12/58 , H04J3/16
CPC分类号： H04M15/57 , H04L12/14 , H04L51/38 , H04M2215/208
摘要： The invention discloses a method for forwarding multimedia messages (MMs) between different multimedia messaging service centers (MMSCs), comprising: a) an originator MMSC receiving a MM submitted by an originator terminal, then editing and generating a routing forward request message for identifying MM information and information relating to the Value Added Service Provider (VASP) service application; b) the originator MMSC sending the routing forward request message generated in step a) to a recipient MMSC; c) the recipient MMSC returning a routing forward response message to the originator MMSC after receiving the routing forward request message; and d) the recipient MMSC delivering the MM according to the MM information and the information relating to the VASP service application contained in the routing forward request message. With this invention, the problem that corresponding charging cannot be implemented when the MMs are forwarded between different MMSCs can be resolved.
摘要翻译：本发明公开了一种用于在不同的多媒体消息服务中心（MMSC）之间转发多媒体消息（MM）的方法，包括：a）发起方MMSC接收由发起方终端提交的MM，然后编辑并产生用于识别MM的路由转发请求消息与增值服务提供商（VASP）服务应用有关的信息和信息; b）发起方MMSC将步骤a）中生成的路由转发请求消息发送到接收者MMSC; c）接收方MMSC在接收到路由转发请求消息后，向发起方MMSC返回路由转发响应消息; 以及d）根据所述MM信息和与所述路由转发请求消息中所包含的VASP服务应用有关的信息来传送MM的接收者MMSC。利用本发明，可以解决在MM在不同MMSC之间转发时不能实现相应计费的问题。

49. 发明授权

US06614371B2 Synchronous data serialization circuit 有权
公开(公告)号：US06614371B2
公开(公告)日：2003-09-02
申请号：US09910436
申请日：2001-07-19
申请人： Bo Zhang
发明人： Bo Zhang
IPC分类号： H03M900
CPC分类号： H03M9/00 , H03K3/356043 , H03K3/356139 , H03K3/3562 , H03K17/04106 , H03K17/693 , H03K2005/00208 , H04J3/047
摘要： In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first data storage circuit. A second data path is provided for processing second data. The second data path includes a second data storage circuit. A multiplexer having a first input coupled to the first data path and a second input coupled to the second data path receives the stored values. The multiplexer includes a select input coupled to a clock signal. A delay circuit is configured to delay storage of the second data in the second data storage circuit, wherein the first data storage circuit stores the first data in response to receiving a first timing signal, and the second data storage circuit stores the second data in response to receiving a second timing signal.

50. 发明授权

US06414822B1 Magnetic microactuator 有权
标题翻译：磁微致动器
公开(公告)号：US06414822B1
公开(公告)日：2002-07-02
申请号：US09315006
申请日：1999-05-19
申请人： Peter Crane , Wayne Allen Bonin , Bo Zhang
发明人： Peter Crane , Wayne Allen Bonin , Bo Zhang
IPC分类号： G11B2120
CPC分类号： G11B21/20 , G11B5/5552
摘要： A dual-stage actuation assembly for a disc drive includes a movable actuator arm controlled by an actuator motor. A suspension assembly is supported by the actuator arm, and includes a flexure. A microactuator is also provided, including a stator attached to the flexure and a rotor supporting the slider, the rotor being movable with respect to the stator in a first horizontal plane generally parallel to a surface of the disc. A vertically arranged magnetic circuit is formed, which in an exemplary embodiment includes a bottom ferromagnetic keeper, a plurality of magnets, a patterned conductive coil and atop ferromagnetic keeper, those elements being vertically arranged in different horizontal planes. The magnets are operable to move laterally and thereby cause movement of the microactuator rotor in the first horizontal plane generally parallel to the surface of the disc in response to circulation of a current through the patterned conductive coil.
摘要翻译：用于盘驱动器的双级致动组件包括由致动器电动机控制的可移动致动器臂。悬架组件由致动器臂支撑并且包括挠曲件。还提供微致动器，其包括附接到挠曲件的定子和支撑滑块的转子，转子可在大致平行于盘的表面的第一水平平面中相对于定子移动。形成垂直布置的磁路，其在一个示例性实施例中包括底部铁磁保持器，多个磁体，图案化导电线圈和顶部铁磁保持器，这些元件垂直布置在不同的水平面中。所述磁体可操作以横向移动，从而响应于电流通过图案化导电线圈的循环而使微致动器转子在第一水平平面中大致平行于盘表面的移动。

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