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41. 发明授权

US07358172B2 Poly filled substrate contact on SOI structure 有权
标题翻译：多晶硅填充衬底接触SOI结构
公开(公告)号：US07358172B2
公开(公告)日：2008-04-15
申请号：US11307762
申请日：2006-02-21
申请人： David M. Dobuzinsky , Byeong Y. Kim , Effendi Leobandung , Munir D. Naeem , Brian L. Tessier
发明人： David M. Dobuzinsky , Byeong Y. Kim , Effendi Leobandung , Munir D. Naeem , Brian L. Tessier
IPC分类号： H01L21/44
CPC分类号： H01L21/84
摘要： Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.
摘要翻译：本文的实施方案提供了一种用于在SOI结构上形成多孔填充衬底接触的方法。该方法在衬底上形成绝缘体，并在绝缘体内形成衬底接触孔。绝缘子表面水平高于最终结构。接下来，执行聚过填料，包括用多晶硅填充衬底接触孔并用多晶硅覆盖绝缘体。具体地，多晶硅的厚度大于基板接触孔的尺寸。接下来，蚀刻多晶硅，其中去除多晶硅的一部分，并且其中衬底接触孔部分地被多晶硅填充。此外，多晶硅的蚀刻在多晶硅的顶部内形成凹形凹部。所述多晶硅的蚀刻不与衬底接触。绝缘体的过剩被抛光到所需的水平。

42. 发明授权

US06806177B2 Method of making self-aligned borderless contacts 失效
标题翻译：制定自主对边无边界联系的方法
公开(公告)号：US06806177B2
公开(公告)日：2004-10-19
申请号：US10719861
申请日：2003-11-21
申请人： Jay W. Strane , Hiroyuki Akatsu , David M. Dobuzinsky
发明人： Jay W. Strane , Hiroyuki Akatsu , David M. Dobuzinsky
IPC分类号： H01L2144
CPC分类号： H01L21/76897
摘要： A method for forming high-density self-aligned contacts and interconnect structures in a semiconductor device. A dielectric layer thick enough to contain both interconnect and contact structures is formed on a substrate. A patterned hardmask is formed on the dielectric layer to define both the interconnect and contact structures. The openings for interconnect features are first formed by partially etching the dielectric layer selective to the hardmask. A second mask (e.g., a resist) is used to define the contact openings, and the dielectric layer is etched through the second mask, also selective to the hardmask, to expose the diffusion regions to be contacted. The patterned hardmask is used to help define the contact openings. Conductive material is then deposited in the openings which results in contacts and interconnects that are self-aligned. By first forming the openings for both interconnect and contacts, savings in processing steps may be obtained.
摘要翻译：一种在半导体器件中形成高密度自对准触点和互连结构的方法。在衬底上形成足够厚以容纳互连和接触结构的电介质层。在电介质层上形成图形化的硬掩模以限定互连和接触结构。用于互连特征的开口首先通过部分蚀刻对硬掩模有选择性的介电层而形成。使用第二掩模（例如抗蚀剂）来限定接触开口，并且通过第二掩模蚀刻电介质层，也可以对硬掩模进行选择，以暴露待接触的扩散区域。图案化的硬掩模用于帮助定义接触开口。然后将导电材料沉积在开口中，这导致自对准的触点和互连。通过首先形成用于互连和接触的开口，可以获得处理步骤的节省。

43. 发明授权

US06570256B2 Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates 有权
标题翻译：碳分级层，用于改善低k电介质与硅衬底的粘附性
公开(公告)号：US06570256B2
公开(公告)日：2003-05-27
申请号：US09910380
申请日：2001-07-20
申请人： Richard A. Conti , Prakash Chimanlal Dev , David M. Dobuzinsky , Daniel C. Edelstein , Gill Y. Lee , Kia-Seng Low , Padraic C. Shafer , Alexander Simpson , Peter Wrschka
发明人： Richard A. Conti , Prakash Chimanlal Dev , David M. Dobuzinsky , Daniel C. Edelstein , Gill Y. Lee , Kia-Seng Low , Padraic C. Shafer , Alexander Simpson , Peter Wrschka
IPC分类号： H01L2348
CPC分类号： H01L21/28185 , H01L21/02126 , H01L21/02274 , H01L21/28194 , H01L21/31633 , H01L23/5329 , H01L23/53295 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.
摘要翻译：公开了一种在衬底上方具有碳分级层的绝缘体层的结构和方法，其中在衬底上方的每个连续的碳分级层中碳的浓度增加。绝缘体包括介电常数小于3.3的低k电介质。碳分级层增加了衬底和绝缘体之间以及绝缘体和导体层之间的粘合性。该结构还可以包括碳分级层之间的稳定界面。更具体地，碳分级层包括邻近基底的第一层，其碳含量在约5％至20％之间，第一层上方的碳含量在约10％至30％之间，第三层在第二层上方具有约20％至40％的碳含量。

44. 发明授权

US06208008B1 Integrated circuits having reduced stress in metallization 失效
标题翻译：集成电路在金属化中具有降低的应力
公开(公告)号：US06208008B1
公开(公告)日：2001-03-27
申请号：US09260702
申请日：1999-03-02
申请人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
发明人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
IPC分类号： H01L2941
CPC分类号： H01L21/76804 , H01L21/32136 , H01L21/76835 , H01L21/76885
摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.
摘要翻译：通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常引起的应力可以通过将与形成为集成电路的一部分的特征相关联的下角在施加外部（即钝化）层之前，例如，互连）。关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化或者沿着垂直侧壁的下部产生锥形间隔物。这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。

45. 发明授权

US5998100A Fabrication process using a multi-layer antireflective layer 失效
标题翻译：使用多层抗反射层的制造工艺
公开(公告)号：US5998100A
公开(公告)日：1999-12-07
申请号：US924652
申请日：1997-09-05
申请人： Tsukasa Azuma , Tokuhisa Ohiwa , Tetsuo Matsuda , David M. Dobuzinsky , Katsuya Okumura
发明人： Tsukasa Azuma , Tokuhisa Ohiwa , Tetsuo Matsuda , David M. Dobuzinsky , Katsuya Okumura
IPC分类号： G03F7/11 , G03F7/09 , H01L21/027 , G03F7/00
CPC分类号： G03F7/091 , H01L21/0276 , Y10S430/151 , Y10S438/945 , Y10S438/95
摘要： A fabrication process includes a step of providing a substrate to be fabricated. A multi-layer antireflective layer is then formed on the substrate. A patterned resist having a thickness less than 850 nanometers is formed on the multi-layer antireflective layer and the substrate is fabricated using the patterned resist as a mask.
摘要翻译：制造工艺包括提供待制造的基板的步骤。然后在基板上形成多层抗反射层。在多层抗反射层上形成厚度小于850纳米的图案化抗蚀剂，并使用图案化的抗蚀剂作为掩模制造基板。

46. 发明授权

US5563105A PECVD method of depositing fluorine doped oxide using a fluorine precursor containing a glass-forming element 失效
标题翻译：使用含有玻璃形成元素的氟前体沉积氟掺杂氧化物的PECVD方法
公开(公告)号：US5563105A
公开(公告)日：1996-10-08
申请号：US316302
申请日：1994-09-30
申请人： David M. Dobuzinsky , Tetsuo Matsuda , Son V. Nguyen , James G. Ryan , Michael Shapiro
发明人： David M. Dobuzinsky , Tetsuo Matsuda , Son V. Nguyen , James G. Ryan , Michael Shapiro
IPC分类号： C23C16/30 , C23C16/40 , C23C16/505 , H01L21/31 , H01L21/316
CPC分类号： H01L21/02131 , C23C16/401 , C23C16/505 , H01L21/02274 , H01L21/31625
摘要： Fluorine-doped oxide is formed that is resistant to water absorption by the use of two sources of silicon, one being the fluorine precursor and the other being available to react with excess fluorine from the fluorine precursor, thereby reducing the number of fluorine radicals in the layer; the fluorine precursor containing a glass-forming element that combines with the other glass constituents to carry into the gas a diatomic radical containing one atom of fluorine and one atom of the glass-forming element.
摘要翻译：形成氟掺杂的氧化物，其通过使用两种硅源而具有耐吸水性，一种是氟前体，另一种可与来自氟前体的过量氟反应，从而减少氟原子的数量层; 含有玻璃形成元素的氟前体与其它玻璃成分结合，将含有一个氟原子和一个玻璃形成元素原子的双原子基团输送到气体中。

47. 发明授权

US5468687A Method of making TA.sub.2 O.sub.5 thin film by low temperature ozone plasma annealing (oxidation) 失效
标题翻译：低温臭氧等离子体退火（氧化）制备TA2O5薄膜的方法
公开(公告)号：US5468687A
公开(公告)日：1995-11-21
申请号：US281399
申请日：1994-07-27
申请人： Dan Carl , David M. Dobuzinsky , Son V. Nguyen , Tue Nguyen
发明人： Dan Carl , David M. Dobuzinsky , Son V. Nguyen , Tue Nguyen
IPC分类号： C30B29/16 , H01B3/00 , H01B3/10 , H01L21/02 , H01L21/205 , H01L21/316 , H01L21/70
CPC分类号： H01L28/40
摘要： A method for low temperature annealing (oxidation) of high dielectric constant Ta.sub.2 O.sub.5 thin films uses an ozone enhanced plasma. The films produced are especially applicable to 64 and 256 Mbit DRAM applications. The ozone enhanced plasma annealing process for thin film Ta.sub.2 O.sub.5 reduces the processing temperature to 400.degree. C. and achieves comparable film quality, making the Ta.sub.2 O.sub.5 films more suitable for Ultra-Large Scale Integration (ULSI) applications (storage dielectric for 64 and 256 Megabit DRAMs with stack capacitor structures, etc.) or others that require low temperature processing. This low temperature process is extendable to other high dc and piezoelectric thin films which may have many other applications.
摘要翻译：高介电常数Ta2O5薄膜的低温退火（氧化）方法使用臭氧增强等离子体。所制作的电影特别适用于64和256 Mbit DRAM应用。用于薄膜Ta2O5的臭氧增强等离子体退火工艺将处理温度降低到400℃，并实现了相当的膜质量，使得Ta2O5膜更适合于超大规模集成（ULSI）应用（64和256兆位DRAM的存储电介质堆叠电容器结构等）或需要低温处理的其他。这种低温工艺可扩展到可能具有许多其它应用的其它高直流和压电薄膜。

48. 发明授权

US5455204A Thin capacitor dielectric by rapid thermal processing 失效
标题翻译：薄电容电介质通过快速热处理
公开(公告)号：US5455204A
公开(公告)日：1995-10-03
申请号：US353760
申请日：1994-12-12
申请人： David M. Dobuzinsky , Son V. Nguyen , Tue Nguyen
发明人： David M. Dobuzinsky , Son V. Nguyen , Tue Nguyen
IPC分类号： H01L21/02 , H01L21/314
CPC分类号： H01L28/86 , H01L21/3144
摘要： The invention provides a continuous rapid thermal process for forming a substantially uniform oxynitride film on fingered three-dimensional silicon structures comprising cleaning of the silicon substrate and growth of silicon oxide in the presence of ozone, nitridation of the silicon oxide layer in the presence of NH.sub.3 and reoxidation of the oxynitride layer in the presence of oxygen.
摘要翻译：本发明提供了一种用于在手指三维硅结构上形成基本上均匀的氮氧化合物膜的连续快速热处理，包括在臭氧存在下清洗硅衬底和生长氧化硅，在NH 3存在下氮化氧化硅层并在氧气存在下再氧化氮氧化物层。

49. 发明授权

US5330935A Low temperature plasma oxidation process 失效
标题翻译：低温等离子体氧化工艺
公开(公告)号：US5330935A
公开(公告)日：1994-07-19
申请号：US915752
申请日：1992-07-21
申请人： David M. Dobuzinsky , David L. Harmon , Srinandan R Kasi , Donald M. Kenney , Son Van Nguyen , Tue Nguyen , Pai-Hung Pan
发明人： David M. Dobuzinsky , David L. Harmon , Srinandan R Kasi , Donald M. Kenney , Son Van Nguyen , Tue Nguyen , Pai-Hung Pan
IPC分类号： C23C8/36 , H01L21/31 , H01L21/316 , H01L21/321 , H01L21/8242 , H01L27/108 , H01L21/02
CPC分类号： H01L21/32105 , H01L21/02238 , H01L21/02252 , H01L21/31662 , Y10S148/118 , Y10S257/90
摘要： A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100.ANG.. An oxide film of uniform thickness is formed by controlling the temperature, RF power, exposure time and oxygen/ozone ratio for thin gate oxide (
摘要翻译：一种在半导体器件的表面上形成薄膜的工艺。该方法包括通过等离子体增强的热氧化形成二氧化硅膜，采用臭氧和氧的混合物，其以反应器室分开产生，体积比约为1-10 / 1，优选约5-7 / 1，在一般低于440℃，优选约350-400℃的温度下进行。该方法用于在场效应晶体管的多晶硅栅上形成侧壁氧化物间隔物。在显着低于常规氧化工艺中使用的温度下实现相对较快的氧化速率，这用于减少掺杂剂从多晶硅的扩散。此外，所得膜表现出低应力，并具有多晶硅栅极的良好的共形台阶覆盖。该方法的另一个用途是生长厚度小于100安培的薄栅氧化物和氧化物 - 氮化物 - 氧化物。通过控制ULSI FET制造中薄栅氧化物（<100 ANGSTROM）应用的温度，RF功率，曝光时间和氧/臭氧比，形成均匀厚度的氧化膜。

50. 发明授权

US5217567A Selective etching process for boron nitride films 失效
标题翻译：氮化硼薄膜的选择性蚀刻工艺
公开(公告)号：US5217567A
公开(公告)日：1993-06-08
申请号：US842663
申请日：1992-02-27
申请人： Donna R. Cote , David M. Dobuzinsky , Son V. Nguyen
发明人： Donna R. Cote , David M. Dobuzinsky , Son V. Nguyen
IPC分类号： H01L21/311 , H01L21/318
CPC分类号： H01L21/318 , H01L21/31116
摘要： Disclosed is a process for etching a film of boron nitride with high selectivity to a layer of silicon dioxide or silicon nitride. The process involves exposing the film to a plasma formed from a mixture of an oxygen-containing gas, such as oxygen, and a small amount of a fluorine-containing gas, such as CF.sub.4. The process provides a high etch rate and anisotropic profiles, as well as good uniformity.
摘要翻译：公开了以高选择性对二氧化硅或氮化硅层蚀刻氮化硼的膜的方法。该方法包括将膜暴露于由含氧气体如氧气和少量含氟气体如CF 4的混合物形成的等离子体。该方法提供了高蚀刻速率和各向异性特性，以及良好的均匀性。

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