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41. 发明申请

US20050272270A1 Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction 审中-公开
公开(公告)号：US20050272270A1
公开(公告)日：2005-12-08
申请号：US11109240
申请日：2005-04-18
申请人： Matthew Metz , Suman Datta , Jack Kavalieros , Mark Doczy , Justin Brask , Uday Shah , Robert Chau
发明人： Matthew Metz , Suman Datta , Jack Kavalieros , Mark Doczy , Justin Brask , Uday Shah , Robert Chau
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/336 , H01L21/8238 , H01L21/8244 , H01L27/11 , H01L29/51 , H01L21/469
CPC分类号： H01L21/28194 , H01L21/3105 , H01L21/823842 , H01L21/823857 , H01L27/11 , H01L29/512 , H01L29/517 , H01L29/66545
摘要： A method for making a semiconductor device is described. That method comprises modifying a first surface, and forming a high-k gate dielectric layer on an unmodified second surface.

42. 发明申请

US20050266619A1 Method for making a semiconductor device with a high-k gate dielectric and a conductor that facilitates current flow across a P/N junction 有权
标题翻译：制造具有高k栅介质的半导体器件和促进电流流过P / N结的导体的方法
公开(公告)号：US20050266619A1
公开(公告)日：2005-12-01
申请号：US10855635
申请日：2004-05-26
申请人： Justin Brask , Jack Kavalieros , Mark Doczy , Matthew Metz , Uday Shah , Chris Barns , Suman Datta , Robert Turkot , Robert Chau
发明人： Justin Brask , Jack Kavalieros , Mark Doczy , Matthew Metz , Uday Shah , Chris Barns , Suman Datta , Robert Turkot , Robert Chau
IPC分类号： H01L21/00 , H01L21/326 , H01L21/336 , H01L21/479 , H01L21/768 , H01L21/8238 , H01L21/84
CPC分类号： H01L29/66545 , H01L21/76895 , H01L21/823842 , H01L21/823857 , H01L21/823871
摘要： A method for making a semiconductor device is described. That method comprises forming on a substrate a first gate dielectric layer that has a first substantially vertical component, then forming a first metal layer on the first gate dielectric layer. After forming on the substrate a second gate dielectric layer that has a second substantially vertical component, a second metal layer is formed on the second gate dielectric layer. In this method, a conductor is formed that contacts both the first metal layer and the second metal layer.
摘要翻译：描述制造半导体器件的方法。该方法包括在衬底上形成具有第一基本垂直分量的第一栅极电介质层，然后在第一栅极电介质层上形成第一金属层。在衬底上形成具有第二基本垂直分量的第二栅介质层之后，在第二栅介质层上形成第二金属层。在该方法中，形成与第一金属层和第二金属层接触的导体。

43. 发明申请

US20050218372A1 Modifying the viscosity of etchants 审中-公开
公开(公告)号：US20050218372A1
公开(公告)日：2005-10-06
申请号：US10816539
申请日：2004-04-01
申请人： Justin Brask , Jack Kavalieros , Mark Doczy , Matthew Metz , Suman Datta , Uday Shah , Robert Chau
发明人： Justin Brask , Jack Kavalieros , Mark Doczy , Matthew Metz , Suman Datta , Uday Shah , Robert Chau
IPC分类号： B44C1/22 , C09K13/00 , C09K13/06 , H01L21/302 , H01L21/3213
CPC分类号： H01L21/32134 , C09K13/06
摘要： Semiconductor integrated circuit structures, such as stacks containing metal layers, may be etched with a modified viscosity etchant. An increased viscosity etchant, for example, may reduce undercutting when a metal film is being etched.

44. 发明申请

US20050214987A1 Replacement gate process for making a semiconductor device that includes a metal gate electrode 有权
标题翻译：用于制造包括金属栅电极的半导体器件的替代栅极工艺
公开(公告)号：US20050214987A1
公开(公告)日：2005-09-29
申请号：US10809853
申请日：2004-03-24
申请人： Uday Shah , Chris Barns , Mark Doczy , Justin Brask , Jack Kavalieros , Matthew Metz , Robert Chau
发明人： Uday Shah , Chris Barns , Mark Doczy , Justin Brask , Jack Kavalieros , Matthew Metz , Robert Chau
IPC分类号： H01L21/00 , H01L21/336 , H01L21/4763 , H01L21/84
CPC分类号： H01L29/66772 , H01L21/84 , H01L29/66545
摘要： A method for making a semiconductor device is described. That method comprises forming a polysilicon layer on a dielectric layer, which is formed on a substrate. The polysilicon layer is etched to generate a patterned polysilicon layer with an upper surface that is wider than its lower surface. The method may be applied, when using a replacement gate process to make transistors that have metal gate electrodes.
摘要翻译：描述制造半导体器件的方法。该方法包括在形成在基板上的电介质层上形成多晶硅层。蚀刻多晶硅层以产生具有比其下表面更宽的上表面的图案化多晶硅层。当使用替换栅极工艺来制造具有金属栅电极的晶体管时，可以应用该方法。

45. 发明申请

US20050148136A1 CMOS DEVICE WITH METAL AND SILICIDE GATE ELECTRODES AND A METHOD FOR MAKING IT 有权
标题翻译：具有金属和硅化物电极的CMOS器件及其制造方法
公开(公告)号：US20050148136A1
公开(公告)日：2005-07-07
申请号：US10748559
申请日：2003-12-29
申请人： Justin Brask , Mark Doczy , Jack Kavalieros , Matthew Metz , Chris Barns , Uday Shah , Suman Datta , Christopher Thomas , Robert Chau
发明人： Justin Brask , Mark Doczy , Jack Kavalieros , Matthew Metz , Chris Barns , Uday Shah , Suman Datta , Christopher Thomas , Robert Chau
IPC分类号： H01L21/8238 , H01L23/48
CPC分类号： H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L27/1203 , H01L29/4975 , H01L29/66545 , Y10S438/926
摘要： A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
摘要翻译：对半导体装置及其形成方法进行说明。半导体器件包括形成在衬底的第一部分上的金属NMOS栅电极和形成在衬底的第二部分上的硅化物PMOS栅电极。

46. 发明申请

US20050101113A1 METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING A METAL GATE ELECTRODE 有权
标题翻译：制造具有金属栅极电极的半导体器件的方法
公开(公告)号：US20050101113A1
公开(公告)日：2005-05-12
申请号：US10704497
申请日：2003-11-06
申请人： Justin Brask , Mark Doczy , Jack Kavalieros , Uday Shah , Matthew Metz , Robert Chau , Robert Turkot
发明人： Justin Brask , Mark Doczy , Jack Kavalieros , Uday Shah , Matthew Metz , Robert Chau , Robert Turkot
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/8238 , H01L29/49 , H01L21/3205
CPC分类号： H01L29/4958 , H01L21/28079 , H01L21/32134 , H01L21/823842
摘要： A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, and forming a first metal layer on a first part of the dielectric layer, leaving a second part of the dielectric layer exposed. After a second metal layer is formed on both the first metal layer and the second part of the dielectric layer, a masking layer is formed on the second metal layer.
摘要翻译：描述制造半导体器件的方法。该方法包括在衬底上形成电介质层，并且在介电层的第一部分上形成第一金属层，留下介电层的第二部分露出。在第一金属层和电介质层的第二部分上形成第二金属层之后，在第二金属层上形成掩模层。

47. 发明申请

US20050048794A1 Method for making a semiconductor device having a high-k gate dielectric 失效
公开(公告)号：US20050048794A1
公开(公告)日：2005-03-03
申请号：US10652796
申请日：2003-08-28
申请人： Justin Brask , Mark Doczy , Scott Hareland , John Barnak , Matthew Metz , Jack Kavalieros , Robert Chau
发明人： Justin Brask , Mark Doczy , Scott Hareland , John Barnak , Matthew Metz , Jack Kavalieros , Robert Chau
IPC分类号： H01L21/28 , H01L21/30 , H01L21/306 , H01L21/316 , H01L29/51 , H01L21/336 , H01L21/3205 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02244 , H01L21/02052 , H01L21/02337 , H01L21/0234 , H01L21/28167 , H01L21/28194 , H01L21/3003 , H01L21/31612 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31683 , H01L21/31691 , H01L29/513 , H01L29/517
摘要： A method for making a semiconductor device is described. That method comprises forming a metal oxide layer on a substrate, converting at least part of the metal oxide layer to a metal layer; and oxidizing the metal layer to generate a metal oxide high-k gate dielectric layer.

48. 发明申请

US20070158702A1 Transistor including flatband voltage control through interface dipole engineering 审中-公开
标题翻译：晶体管包括通过接口偶极工程的平带电压控制
公开(公告)号：US20070158702A1
公开(公告)日：2007-07-12
申请号：US11322827
申请日：2005-12-30
申请人： Mark Doczy , Matthew Metz , Justin Brask , Robert Chau , Gilbert Dewey
发明人： Mark Doczy , Matthew Metz , Justin Brask , Robert Chau , Gilbert Dewey
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/785 , H01L29/4908
摘要： A transistor comprising a semiconductor including a source, a drain, and a channel interposed between the source and the drain; a first dielectric layer having a first thickness, the first dielectric layer being positioned on the channel; a second dielectric layer having a second thickness, the second dielectric layer being positioned on the first dielectric layer; and a gate electrode on the second dielectric layer, wherein the transistor gate is made of a mid-gap metal. A process comprising depositing a first dielectric layer on at least one surface of a semiconductor layer; depositing a second dielectric layer on the first dielectric layer; depositing a layer of mid-gap metal on the second dielectric layer; and patterning and etching the first dielectric layer, the second dielectric layer and the layer of mid-gap metal to create a gate electrode separated from the substrate by a first dielectric and a second dielectric. Other embodiments are disclosed and claimed.
摘要翻译：一种晶体管，包括：半导体，包括源极，漏极和介于源极和漏极之间的沟道; 具有第一厚度的第一介电层，所述第一介电层位于所述通道上; 具有第二厚度的第二介电层，所述第二介电层位于所述第一介电层上; 以及第二介质层上的栅电极，其中晶体管栅极由中间间隙金属制成。一种方法，包括在半导体层的至少一个表面上沉积第一介电层; 在所述第一电介质层上沉积第二电介质层; 在所述第二电介质层上沉积中间间隙金属层; 以及对第一电介质层，第二电介质层和中间间隙金属层进行图案化和蚀刻以产生通过第一电介质和第二电介质与衬底分离的栅电极。公开和要求保护其他实施例。

49. 发明申请

US20070145498A1 DEVICE WITH SCAVENGING SPACER LAYER 有权
标题翻译：装置与SCAVENGING间隔层
公开(公告)号：US20070145498A1
公开(公告)日：2007-06-28
申请号：US11320305
申请日：2005-12-27
申请人： Matthew Metz , Mark Doczy , Justin Brask , Robert Chau
发明人： Matthew Metz , Mark Doczy , Justin Brask , Robert Chau
IPC分类号： H01L29/94
CPC分类号： H01L29/0847 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66636
摘要： Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen-scavenging spacer layer on side walls of the high-k gate dielectric layer and metal gate may reduce such oxidation during high temperature processes.
摘要翻译：本发明的实施例提供一种具有金属栅极，高k栅极电介质层和在高k栅极电介质层下面的衬底的氧化减少的器件。在高k栅极电介质层和金属栅极的侧壁上的氧气清除间隔层可以在高温过程中减少这种氧化。

50. 发明申请

US20070138565A1 Extreme high mobility CMOS logic 有权
标题翻译：极高移动性CMOS逻辑
公开(公告)号：US20070138565A1
公开(公告)日：2007-06-21
申请号：US11305452
申请日：2005-12-15
申请人： Suman Datta , Mantu Hudait , Mark Doczy , Jack Kavalleros , Majumdar Amlan , Justin Brask , Been-Yih Jin , Matthew Metz , Robert Chau
发明人： Suman Datta , Mantu Hudait , Mark Doczy , Jack Kavalleros , Majumdar Amlan , Justin Brask , Been-Yih Jin , Matthew Metz , Robert Chau
IPC分类号： H01L29/94
CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。

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