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41. 发明申请

US20120112154A1 IN VIA FORMED PHASE CHANGE MEMORY CELL WITH RECESSED PILLAR HEATER 失效
标题翻译：通过形成相位改变记忆细胞与被加热的支柱加热器
公开(公告)号：US20120112154A1
公开(公告)日：2012-05-10
申请号：US13350967
申请日：2012-01-16
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L47/00
CPC分类号： H01L45/143 , H01L27/2436 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material.
摘要翻译：一种用于制造包括多个通孔相变存储单元的相变存储器件的方法包括：形成由导电材料形成的支柱加热器，沿着与要连接到存取电路的导电触点阵列相对应的衬底的接触表面沿着围绕柱加热器的衬底的暴露区域形成电介质层，在电介质层之上形成层间电介质（ILD）层，将通孔蚀刻到电介质层，每个通孔对应于每个立柱加热器，使得上表面每个立柱加热器暴露在每个通孔内，使每个立柱加热器凹陷，在每个凹槽加热器上的每个通孔中沉积相变材料，使每个通孔内的相变材料凹陷，并且在相变材料上的通孔内形成顶部电极。

42. 发明授权

US08105859B2 In via formed phase change memory cell with recessed pillar heater 有权
标题翻译：在通孔形成相位改变存储单元与凹柱加热器
公开(公告)号：US08105859B2
公开(公告)日：2012-01-31
申请号：US12556198
申请日：2009-09-09
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L21/00 , H01L45/00
CPC分类号： H01L45/143 , H01L27/2436 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material.
摘要翻译：一种用于制造包括多个通孔相变存储单元的相变存储器件的方法包括：形成由导电材料形成的支柱加热器，沿着与要连接到存取电路的导电触点阵列相对应的衬底的接触表面沿着围绕柱加热器的衬底的暴露区域形成电介质层，在电介质层之上形成层间电介质（ILD）层，将通孔蚀刻到电介质层，每个通孔对应于每个立柱加热器，使得上表面每个立柱加热器暴露在每个通孔内，使每个立柱加热器凹陷，在每个凹槽加热器上的每个通孔中沉积相变材料，使每个通孔内的相变材料凹陷，并且在相变材料上的通孔内形成顶部电极。

43. 发明申请

US20110037042A1 PHASE CHANGE MEMORY DEVICE WITH PLATED PHASE CHANGE MATERIAL 有权
公开(公告)号：US20110037042A1
公开(公告)日：2011-02-17
申请号：US12541595
申请日：2009-08-14
申请人： Matthew J. Breitwisch , Eric A. Joseph , Alejandro G. Schrott , Xiaoyan Shao
发明人： Matthew J. Breitwisch , Eric A. Joseph , Alejandro G. Schrott , Xiaoyan Shao
IPC分类号： H01L47/00 , H01L21/16
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1608 , H01L45/1683 , H01L45/1691
摘要： A method for fabricating a phase change memory device including memory cells includes patterning a via to a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, lining each via with a conformal conductive seed layer to the contact surface, forming a dielectric layer covering the conductive seed layer, and etching a center region of each via to the contact surface to expose the conformal conductive seed layer at the contact surface. The method further includes electroplating phase change material on exposed portions of the conformal conductive seed layer, recessing the phase change material within the center region forming a conductive material that remains conductive upon oxidation, on the recessed phase change material, oxidizing edges of the conformal conductive seed layer formed along sides of each via, and forming a top electrode over each memory cell.

44. 发明申请

US20100078617A1 METHOD TO REDUCE A VIA AREA IN A PHASE CHANGE MEMORY CELL 有权
标题翻译：减少相变记忆体中的通风区域的方法
公开(公告)号：US20100078617A1
公开(公告)日：2010-04-01
申请号：US12243759
申请日：2008-10-01
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Yu Zhu
IPC分类号： H01L29/04 , H01L21/06 , H01L21/44
CPC分类号： H01L45/144 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/1683
摘要： A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer.
摘要翻译：存储单元结构和形成这种结构的方法。该方法部分地包括在底部电极的中心上形成氧化层内的通孔。该方法包括沿通孔的侧壁沉积通孔间隔物并氧化通孔间隔物。通孔间隔件由具有至少一个半的起珠床比的材料组成，并且当被氧化时是绝缘体。在氧化期间通孔间隔物的膨胀减小了通孔面积。或者，该方法部分地包括在底部电极的中心之上在第一层内形成通孔。第一层具有至少一个半的Pilling-Bedworth比，并且当被氧化时是绝缘体。该方法还包括在第一层中氧化通孔的侧壁的至少一部分。

45. 发明授权

US07560721B1 Phase change material with filament electrode 有权
标题翻译：相变材料与灯丝电极
公开(公告)号：US07560721B1
公开(公告)日：2009-07-14
申请号：US12035237
申请日：2008-02-21
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Gerhard Ingmar Meijer
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Gerhard Ingmar Meijer
IPC分类号： H01L47/00
CPC分类号： H01L45/141 , G11C13/0004 , G11C13/0007 , G11C2213/52 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/1246 , H01L45/145
摘要： The present invention, in one embodiment, provides a memory device that includes a phase change memory cell; a first electrode; and a layer of filamentary resistor material positioned between the phase change memory cell and the first electrode, wherein at least one bistable conductive filamentary pathway is present in at least a portion of the layer of filamentary resistor material that provides electrical communication between the phase change memory cell and the first electrode.
摘要翻译：本发明在一个实施例中提供了一种包括相变存储单元的存储器件; 第一电极; 以及位于所述相变存储器单元和所述第一电极之间的丝状电阻材料层，其中在所述丝状电阻器材料层的至少一部分中存在至少一个双稳态导电丝状通道，其提供所述相变存储器电池和第一电极。

46. 发明申请

US20090111228A1 SELF ALIGNED RING ELECTRODES 有权
标题翻译：自对准环电极
公开(公告)号：US20090111228A1
公开(公告)日：2009-04-30
申请号：US11924073
申请日：2007-10-25
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Brandon Yee
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Brandon Yee
IPC分类号： H01L21/33
CPC分类号： H01L21/76843 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/148 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a sidewall of the via and the at least one metal stud; recessing an upper surface of the at least one metal stud below an upper surface of the first dielectric layer to provide at least one recessed metal stud; and forming a second dielectric atop the at least one recessed metal stud, wherein an upper surface of the electrically conductive liner is exposed.
摘要翻译：本发明在一个实施例中提供了一种制造电极的方法，其包括提供定位在延伸到第一介电层中的通孔中的至少一个金属柱，其中导电衬垫定位在通孔的至少侧壁和在最少一个金属螺柱; 将所述至少一个金属螺柱的上表面凹陷在所述第一介电层的上表面下方，以提供至少一个凹入的金属柱; 以及在所述至少一个凹入的金属螺柱的顶部上形成第二电介质，其中所述导电衬垫的上表面被暴露。

47. 发明授权

US07485487B1 Phase change memory cell with electrode 有权
标题翻译：带电极的相变存储单元
公开(公告)号：US07485487B1
公开(公告)日：2009-02-03
申请号：US11970207
申请日：2008-01-07
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683 , H01L45/1691
摘要： The present invention in one embodiment provides a method of forming a memory device including providing a first dielectric layer including at least one via containing a metal stud; providing a second dielectric layer atop the first dielectric layer; recessing the metal stud to expose a sidewall of the via; etching the sidewall of the via in the first dielectric layer with a isotropic etch step to produce an undercut region extending beneath a portion of the second dielectric layer; forming a conformal insulating layer on at least the portion of the second dielectric layer overlying the undercut region to provide a keyhole; etching the conformal insulating layer with an anisotropic etch to provide a collar that exposes the metal stud; forming a barrier metal within the collar in contact with the metal stud; and forming a phase change material in contact with the barrier metal.
摘要翻译：本发明在一个实施例中提供了一种形成存储器件的方法，该存储器件包括：提供包括至少一个通孔的第一介电层，所述通孔包含金属螺柱; 在所述第一电介质层的顶部提供第二电介质层; 使金属螺柱凹陷以暴露通孔的侧壁; 用各向同性蚀刻步骤蚀刻第一介电层中的通孔的侧壁，以产生在第二介电层的一部分下方延伸的底切区域; 在覆盖所述底切区域的所述第二介电层的至少一部分上形成保形绝缘层以提供锁眼; 用各向异性蚀刻蚀刻保形绝缘层以提供露出金属螺柱的套环; 在所述套环内形成与所述金属螺栓接触的阻挡金属; 并形成与阻挡金属接触的相变材料。

48. 发明授权

US08017432B2 Deposition of amorphous phase change material 有权
标题翻译：沉积非晶相变材料
公开(公告)号：US08017432B2
公开(公告)日：2011-09-13
申请号：US12684185
申请日：2010-01-08
申请人： Chung Hon Lam , Alejandro G. Schrott
发明人： Chung Hon Lam , Alejandro G. Schrott
IPC分类号： H01L21/06
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/144 , H01L45/1616 , H01L45/1641 , H01L45/1683
摘要： A method for formation of a phase change memory (PCM) cell includes depositing amorphous phase change material in a via hole, the via hole comprising a bottom and a top, such that the amorphous phase change material is grown on an electrode located at the bottom of the via hole; melt-annealing the amorphous phase change material; and crystallizing the phase change material starting at the electrode at the bottom of the via hole and ending at the top of the via hole.
摘要翻译：形成相变存储器（PCM）单元的方法包括在通孔中沉积非晶相变材料，该通孔包括底部和顶部，使得非晶相变材料在位于底部的电极上生长的通孔; 对非晶相变材料进行熔融退火; 并且从通孔底部的电极开始并且以通孔的顶部结束，使相变材料结晶。

49. 发明授权

US08383501B2 Vertical field effect transistor arrays and methods for fabrication thereof 有权
标题翻译：垂直场效应晶体管阵列及其制造方法
公开(公告)号：US08383501B2
公开(公告)日：2013-02-26
申请号：US13185055
申请日：2011-07-18
申请人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L21/28
CPC分类号： H01L21/823487 , H01L27/088
摘要： Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
摘要翻译：垂直场效应晶体管半导体结构和用于制造垂直场效应晶体管半导体结构的方法提供半导体柱阵列。半导体柱阵列中的每个半导体柱的每个垂直部分具有大于与相邻半导体柱的间隔距离的线宽。或者，阵列可以包括具有不同线宽的半导体柱，任选地在上述线宽和间隔距离限制的上下文中。用于制造半导体柱阵列的方法使用最小光刻尺寸的柱掩模层，其在被用作蚀刻掩模之前用至少一个间隔层环形增强。

50. 发明申请

US20130001499A1 Compressive Structure for Enhancing Contact of Phase Change Material Memory Cells 审中-公开
标题翻译：用于增强相变材料记忆单元接触的压缩结构
公开(公告)号：US20130001499A1
公开(公告)日：2013-01-03
申请号：US13171210
申请日：2011-06-28
申请人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L45/00 , H01L21/06 , H01L21/62
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1616 , H01L45/1683
摘要： A process for manufacturing a PCM device comprises forming a dielectric, producing a via in the dielectric starting at an area on the surface of the dielectric by forming a via opening in the area and extending the opening into the dielectric toward and then terminating at an electrode comprising a first electrode in the dielectric. We form a spacer layer contiguous with the side walls of the via and fill the via with a PCM. We then remove the surface of the dielectric to leave a PCM cusp at the opening of the via, cap the PCM cusp with a low density capping film; densify the PCM and capping film to obtain a high density capping film that exerts compressive pressure on the high density PCM in a direction toward the first electrode to enhance electrical contact between the PCM and the first electrode.
摘要翻译：一种用于制造PCM器件的方法包括形成电介质，通过在该区域中形成通孔开口，在电介质的表面上的区域开始在电介质中产生通孔，并将该开口延伸到电介质中然后终止于电极包括电介质中的第一电极。我们形成与通孔的侧壁相邻的间隔层，并用PCM填充通孔。然后我们将电介质的表面去除，以在通孔的开口处留下PCM尖点，用低密度封盖膜盖住PCM尖端; 密封PCM和封盖膜以获得高密度封盖膜，其在朝向第一电极的方向上对高密度PCM施加压缩压力，以增强PCM与第一电极之间的电接触。

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