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41. 发明授权

US06185702B2 Method and system for process state management using checkpoints 失效
标题翻译：使用检查点的进程状态管理方法和系统
公开(公告)号：US06185702B2
公开(公告)日：2001-02-06
申请号：US09012463
申请日：1998-01-23
申请人： Toshio Shirakihara , Hideaki Hirayama , Kiyoko Sato , Tatsunori Kanai
发明人： Toshio Shirakihara , Hideaki Hirayama , Kiyoko Sato , Tatsunori Kanai
IPC分类号： G06F1110
CPC分类号： G06F11/1438
摘要： A process state management scheme capable of acquiring process states consistently even in a case where a new process is generated from some process, while using the synchronous checkpointing method. This scheme prohibits a new process generation during a process state acquisition, which can be realized by judging whether a process generation request by a first process for generating a second process is prior to a process state acquisition request or not, and generating the second process from the first process accordingly. This scheme also prohibits a process state acquisition during a new process generation, which can be realized by acquiring a process state at each of the first and second processes after a notice of the identifier of the second process from the first process is received, when a notice of the identifier of the second process from the second process is prior to the notice from the first process.
摘要翻译：即使在使用同步检查点方法的情况下，即使在从某个处理生成新处理的情况下，也能够一致地获取处理状态的处理状态管理方案。该方案禁止在处理状态获取期间的新的处理生成，其可以通过判断通过用于生成第二处理的第一处理的处理生成请求是否在处理状态获取请求之前来实现，并且从第相应的第一个过程。该方案还禁止在新进程生成期间的进程状态获取，这可以通过在从第一进程获得第二进程的标识符的通知被接收到之后获取第一和第二进程中的每一个处理状态来实现，来自第二进程的第二进程的标识符的通知在从第一进程通知之前。

42. 发明授权

US5862403A Continuous data server apparatus and data transfer scheme enabling multiple simultaneous data accesses 失效
标题翻译：连续数据服务器设备和数据传输方案支持多次同时访问数据
公开(公告)号：US5862403A
公开(公告)日：1999-01-19
申请号：US603759
申请日：1996-02-16
申请人： Tatsunori Kanai , Shigehiro Asano , Takeshi Aikawa , Shinya Amano
发明人： Tatsunori Kanai , Shigehiro Asano , Takeshi Aikawa , Shinya Amano
IPC分类号： G06F3/06 , G06F11/10 , H04L12/54 , H04L12/861 , H04L12/883 , G06F15/02
CPC分类号： H04L12/5693 , G06F11/1076 , G06F11/1088 , G06F3/0601 , H04L49/90 , H04L49/9021 , H04L49/9047 , H04L49/9073 , G06F2003/0692
摘要： A continuous data server apparatus incorporating a plurality of buffer memory units for storing the continuous data read out by the data memory control units and to be given to the communication control unit, at least one buffer memory unit being provided dedicatedly for each combination of one data memory control unit group formed by at least one data memory control unit and one communication control unit group formed by at least one communication control unit. The apparatus may further incorporate a plurality of calculation units connected in series, where each calculation unit is connected between corresponding one data memory control unit group and at least one buffer memory unit, and carrying out a prescribed calculation processing. The continuous data can be arranged over a plurality of data memory control units in word units, such that the data memory control units read out the continuous data in block units, the buffer memory units store the continuous data in block units, and the communication control unit transfers the continuous data obtained by reading out data the buffer memory units sequentially in word units.
摘要翻译：一种连续数据服务器装置，其包括多个缓冲存储器单元，用于存储由数据存储器控制单元读出的连续数据，并被提供给通信控制单元，至少一个缓冲存储器单元专门为一个数据的每个组合提供由至少一个数据存储器控制单元形成的存储器控制单元组和由至少一个通信控制单元形成的一个通信控制单元组。该装置还可以包括串联连接的多个计算单元，其中每个计算单元连接在相应的一个数据存储器控制单元组和至少一个缓冲存储器单元之间，并执行规定的计算处理。连续数据可以以单位单位布置在多个数据存储器控制单元上，使得数据存储器控制单元以块为单位读出连续数据，缓冲存储器单元以块为单位存储连续数据，并且通信控制单元通过以字为单位顺序地读出缓冲存储器单元的数据而获得的连续数据。

43. 发明授权

US08892810B2 Semiconductor device and memory protection method 有权
标题翻译：半导体器件和存储器保护方法
公开(公告)号：US08892810B2
公开(公告)日：2014-11-18
申请号：US13399185
申请日：2012-02-17
申请人： Hiroto Nakai , Tatsunori Kanai , Kenichi Maeda
发明人： Hiroto Nakai , Tatsunori Kanai , Kenichi Maeda
IPC分类号： G06F12/02 , G06F9/54
CPC分类号： G06F9/524 , G06F9/544 , G06F12/0246
摘要： According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.
摘要翻译：根据一个实施例，半导体器件包括处理器和存储器件。存储器件具有非易失性半导体存储器件，并且被配置为用作处理器的主存储器。当处理器执行多个程序时，处理器管理作为各个程序的工作流程执行程序所需的信息，并创建表，其保持各工作组所需的信息和各条信息的地址之间的关系在存储器件中，用于各个工作台。处理器参考相应工作台的相应表访问存储器件。

44. 发明申请

US20120246397A1 STORAGE DEVICE MANAGEMENT DEVICE AND METHOD FOR MANAGING STORAGE DEVICE 有权
标题翻译：存储设备管理设备和用于管理存储设备的方法
公开(公告)号：US20120246397A1
公开(公告)日：2012-09-27
申请号：US13491824
申请日：2012-06-08
申请人： Hiroto NAKAI , Tatsunori Kanai
发明人： Hiroto NAKAI , Tatsunori Kanai
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0638
摘要： According to one embodiment, a storage device management device is connected to a random access memory and a first storage device. When the random access memory includes a free region sufficient to store write data, the write data is stored onto the random access memory. Data on the random access memory selected in the descending order of elapsed time from the last access is sequentially copied onto the first storage device, and a region in the random access memory which has stored the copied data is released. When stored on the random access memory, the read data is read from the random access memory to the processor. When stored on the first storage device, the read data is copied onto the random access memory and read from the random access memory to the processor.
摘要翻译：根据一个实施例，存储设备管理设备连接到随机存取存储器和第一存储设备。当随机存取存储器包括足以存储写入数据的空闲区域时，写入数据被存储到随机存取存储器中。按照从最后访问经过的时间的降序选择的随机存取存储器上的数据被顺序复制到第一存储设备上，并且释放存储了复制数据的随机存取存储器中的区域。当存储在随机存取存储器中时，将读取的数据从随机存取存储器读取到处理器。当存储在第一存储设备上时，将读取的数据复制到随机存取存储器中并从随机存取存储器读取到处理器。

45. 发明授权

US08166356B2 Memory system and memory access method 有权
标题翻译：内存系统和内存访问方式
公开(公告)号：US08166356B2
公开(公告)日：2012-04-24
申请号：US12393251
申请日：2009-02-26
申请人： Tatsunori Kanai
发明人： Tatsunori Kanai
IPC分类号： G06F11/00
CPC分类号： G06F11/1008
摘要： A memory system has a redundancy coding circuit that performs redundancy coding process for write data, an inverter circuit which inverts values of individual bits of the data that has resulted from the redundancy coding process, a selector which selects the data that has resulted from the redundancy coding process or data that has been inverted by the inverter circuit based on a selecting signal, a memory which stores the selected data, a comparator which compares data read from the memory with the selected data and outputs a comparison result, a write control circuit which generates the selecting signal based on the comparison results, and a redundancy decoding circuit that performs a redundancy decoding process for data read from the memory to output the processed data.
摘要翻译：存储器系统具有对写入数据执行冗余编码处理的冗余编码电路，对从冗余编码处理得到的数据的各位的值进行反转的反相器电路，选择由冗余产生的数据的选择器编码处理或基于选择信号被逆变器电路反相的数据，存储所选择的数据的存储器，将从存储器读取的数据与所选择的数据进行比较并输出比较结果的比较器，写入控制电路，基于比较结果生成选择信号，以及冗余解码电路，对从存储器读取的数据进行冗余解码处理，输出处理后的数据。

46. 发明授权

US07877751B2 Maintaining level heat emission in multiprocessor by rectifying dispatch table assigned with static tasks scheduling using assigned task parameters 失效
标题翻译：通过使用分配的任务参数整理分配有静态任务调度的调度表来维持多处理器中的发热量
公开(公告)号：US07877751B2
公开(公告)日：2011-01-25
申请号：US11232984
申请日：2005-09-23
申请人： Seiji Maeda , Tatsunori Kanai
发明人： Seiji Maeda , Tatsunori Kanai
IPC分类号： G06F9/46 , G06F1/00
CPC分类号： G06F9/4893 , G06F1/206 , G06F1/329 , Y02D10/24
摘要： According to an aspect of the present invention, heat emissions of processors are level among the processors, and it is possible to suppress occurrence of stop of process due to overheating. The control IC assigns tasks to the processors, and thereafter rectifies an assignment result such that temperatures of the processors become almost level among the processors, on the basis of the temperatures of the processors obtained by temperature sensors. This structure enables level heat emissions among the processors, and suppresses occurrence of stop of process due to overheating.
摘要翻译：根据本发明的一个方面，处理器的热排放是处理器之间的水平，并且可以抑制由于过热而导致的处理停止的发生。控制IC将任务分配给处理器，然后基于由温度传感器获得的处理器的温度，对处理器中的处理器的温度几乎达到一定程度的分配结果进行整流。这种结构使得处理器之间能够发生热量排放，并且抑制由于过热而导致的过程停止的发生。

47. 发明授权

US07770176B2 Multiprocessor computer and program 失效
标题翻译：多处理器计算机和程序
公开(公告)号：US07770176B2
公开(公告)日：2010-08-03
申请号：US11233026
申请日：2005-09-23
申请人： Seiji Maeda , Tatsunori Kanai
发明人： Seiji Maeda , Tatsunori Kanai
IPC分类号： G06F9/46 , G06F1/00
CPC分类号： G06F9/4893 , G06F1/206 , Y02D10/24
摘要： According to an aspect of the present invention, the processor temperatures can be leveled among processors, thereby suppressing the occurrence of stop of processing due to overheating. For example, on the basis of the temperatures of the processors sensed by temperature sensors, the control IC assigns the processor whose temperature is the lowest to the task whose heat emission is the highest. This makes it possible to level the processor temperatures among processors and suppress occurrence of stop of processing due to overheating.
摘要翻译：根据本发明的一个方面，可以在处理器之间调整处理器温度，从而抑制由于过热而导致的处理停止的发生。例如，基于由温度传感器感测到的处理器的温度，控制IC将温度最低的处理器分配给发热最高的任务。这使得可以对处理器之间的处理器温度进行调整，并抑制由于过热而导致的处理停止的发生。

48. 发明申请

US20090319867A1 MEMORY SYSTEM AND MEMORY ACCESS METHOD 有权
标题翻译：存储系统和存储器访问方法
公开(公告)号：US20090319867A1
公开(公告)日：2009-12-24
申请号：US12393251
申请日：2009-02-26
申请人： Tatsunori Kanai
发明人： Tatsunori Kanai
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1008
摘要： A memory system has a redundancy coding circuit that performs redundancy coding process for write data, an inverter circuit which inverts values of individual bits of the data that has resulted from the redundancy coding process, a selector which selects the data that has resulted from the redundancy coding process or data that has been inverted by the inverter circuit based on a selecting signal, a memory which stores the selected data, a comparator which compares data read from the memory with the selected data and outputs a comparison result, a write control circuit which generates the selecting signal based on the comparison results, and a redundancy decoding circuit that performs a redundancy decoding process for data read from the memory to output the processed data.
摘要翻译：存储器系统具有对写入数据执行冗余编码处理的冗余编码电路，对从冗余编码处理得到的数据的各位的值进行反转的反相器电路，选择由冗余产生的数据的选择器编码处理或基于选择信号被逆变器电路反相的数据，存储所选择的数据的存储器，将从存储器读取的数据与所选择的数据进行比较并输出比较结果的比较器，写入控制电路，基于比较结果生成选择信号，以及冗余解码电路，对从存储器读取的数据进行冗余解码处理，输出处理后的数据。

49. 发明授权

US07441248B2 Data transfer scheme using caching technique for reducing network load 失效
标题翻译：数据传输方案采用缓存技术减少网络负载
公开(公告)号：US07441248B2
公开(公告)日：2008-10-21
申请号：US10253517
申请日：2002-09-25
申请人： Hideaki Sato , Tatsunori Kanai , Hideki Yoshida , Toshibumi Seki , Kenichiro Yoshii , Takayuki Miyazawa , Yasuhiro Kimura , Haruhiko Toyama
发明人： Hideaki Sato , Tatsunori Kanai , Hideki Yoshida , Toshibumi Seki , Kenichiro Yoshii , Takayuki Miyazawa , Yasuhiro Kimura , Haruhiko Toyama
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00 , G06F15/16
CPC分类号： H04L67/2819 , H04L67/2842 , H04L67/288 , H04L69/22 , H04L69/329
摘要： In a data transfer device, presence/absence of a prescribed header in the received request message is analyzed, and information indicating the presence/absence of the prescribed header, or information indicating either presence or absence of the prescribed header when the prescribed header is either present or absent as a result of analysis is stored. Then, when a reply message corresponding to the request message is received, the presence/absence of the prescribed header is checked by referring to the stored information, and the reply message is transferred according to a result of checking.
摘要翻译：在数据传送装置中，分析所接收到的请求消息中规定的报头的存在/不存在，以及指示规定标题的存在/不存在的信息，或者当规定报头是作为分析结果存在或不存在。然后，当接收到与请求消息对应的回复消息时，通过参考所存储的信息来检查规定报头的存在/不存在，并且根据检查结果传送回复消息。

50. 发明申请

US20080155153A1 Device control apparatus 失效
标题翻译：设备控制装置
公开(公告)号：US20080155153A1
公开(公告)日：2008-06-26
申请号：US11896848
申请日：2007-09-06
申请人： Kenichiro Yoshii , Tatsunori Kanai , Hiroshi Yao
发明人： Kenichiro Yoshii , Tatsunori Kanai , Hiroshi Yao
IPC分类号： G06F13/24
CPC分类号： G06F21/575 , G06F9/45537 , G06F9/4812
摘要： A device control apparatus includes a processor that operates according to software, a storage unit that stores privileged software which manages an interrupt to the processor from a device included in the device control apparatus, an OS storage unit that stores an Operation System for calling the privileged software from the storage unit when an interrupt from the device is detected during an execution of the software, a detecting unit that detects an interrupt to the Operation System from the device while the Operation System is operating on the processor, a judging unit that judges whether the Operation System has called the privileged software from the storage unit in a first predetermined time from detection of the interrupt to the Operation System from the device, and a resetting unit that resets the processor when the judging unit judges that the Operation System has not called the privileged software from the storage unit.
摘要翻译：一种设备控制装置，包括根据软件进行操作的处理器，存储单元，其存储从包含在所述设备控制装置中的设备向所述处理器管理中断的特许软件; OS存储单元，其存储用于呼叫所述特权的操作系统在软件执行期间检测到来自设备的中断时来自存储单元的软件;检测单元，其在所述操作系统在所述处理器上操作时从所述设备检测到所述操作系统的中断;判断单元，其判断是否所述操作系统在从所述设备检测到所述中断到所述操作系统的第一预定时间中从所述存储单元中调用所述特权软件;以及复位单元，当所述判断单元判断所述操作系统未被调用时，复位所述处理器来自存储单元的特权软件。

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