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41. 发明授权

US06940519B2 Graphics processor, graphics card and graphics processing system 失效
标题翻译：图形处理器，显卡和图形处理系统
公开(公告)号：US06940519B2
公开(公告)日：2005-09-06
申请号：US10619435
申请日：2003-07-16
申请人： Takahiro Saito , Atsushi Kunimatsu
发明人： Takahiro Saito , Atsushi Kunimatsu
IPC分类号： G06T15/00 , G09G5/00 , G09G5/36 , G09G5/377 , G06F12/06
CPC分类号： G06T15/80 , G06T2200/28
摘要： A graphics processor includes a shading processing section which subjects pixel data to a shading process, a first path which permits map data and texture data output from a video memory to be input to the shading processing section, a second path which permits pixel data output from the shading processing section to be output to the video memory, and a third path which permits pixel data output from a pixel expanding section to be input to the shading processing section. Further, the third path permits pixel data output from the video memory to be input to the shading processing section instead of the pixel data output from the pixel expanding section.
摘要翻译：图形处理器包括将像素数据进行阴影处理的着色处理部分，允许从视频存储器输出的地图数据和纹理数据输入到阴影处理部分的第一路径，允许从将要输出到视频存储器的阴影处理部分和允许从像素扩展部分输出的像素数据输入到阴影处理部分的第三路径。此外，第三路径允许从视频存储器输出的像素数据被输入到阴影处理部分，而不是从像素扩展部分输出的像素数据。

42. 发明申请

US20050174348A1 Image processing device, image processing program, recording medium recording the program, image processing method, and shading information acquisition device 审中-公开
标题翻译：图像处理装置，图像处理程序，记录程序的记录介质，图像处理方法和着色信息获取装置
公开(公告)号：US20050174348A1
公开(公告)日：2005-08-11
申请号：US10514896
申请日：2003-10-29
申请人： Yoshiyuki Sakaguchi , Shintaro Takemura , Shigeru Mitsui , Yasunobu Yamauchi , Atsushi Kunimatsu
发明人： Yoshiyuki Sakaguchi , Shintaro Takemura , Shigeru Mitsui , Yasunobu Yamauchi , Atsushi Kunimatsu
IPC分类号： G06T15/04 , G06T15/80 , G06T19/20 , G06T15/50 , G06T15/60
CPC分类号： G06T15/80 , G06T15/50
摘要： Disclosed is an image processing apparatus, comprising a shading-information acquisition device 1 for picking up an image of an actual sample, a shading-information calculation section 201 for calculating shading information using the image acquired by the shading-information acquisition device 1, and storing the calculated shading information in a shading-information storage section 101, in association with the value of a parameter including an image pickup condition during the pickup of the image, a parameter calculation section 203 for calculating a specific value of the parameter at given position of a virtual 3-dimensional model, a shading-information read section 204 for allowing the shading-information storage section 101 to read the shading information corresponding to the calculated parameter value therethrough, and a shading processing section 206 for calculating a brightness value at a target position HP of the virtual 3-dimensional model, using the read shading information and a texture stored in a texture storage section 103.
摘要翻译：公开了一种图像处理装置，包括：用于拾取实际样本的图像的着色信息获取装置1，使用由遮蔽信息获取装置1获取的图像计算着色信息的着色信息计算部201;以及将所计算的阴影信息存储在阴影信息存储部分101中，与在图像拾取期间包括图像拾取条件的参数的值相关联;参数计算部分203，用于计算给定位置处的参数的特定值虚线3维模型的遮蔽信息读取部分204，用于允许着色信息存储部分101读取对应于所计算的参数值的阴影信息;以及阴影处理部分206，用于计算亮度值目标位置HP的虚拟三维模型，使用读取阴影信息 n和存储在纹理存储部分103中的纹理。

43. 发明授权

US06388672B1 Graphic translate engine, floating point arithmetic unit and floating point multiply-add calculation unit 失效
标题翻译：图形翻译引擎，浮点运算单元和浮点乘法运算单元
公开(公告)号：US06388672B1
公开(公告)日：2002-05-14
申请号：US08792022
申请日：1997-01-31
申请人： Nobuhiro Ide , Atsushi Kunimatsu , Maki Ueno
发明人： Nobuhiro Ide , Atsushi Kunimatsu , Maki Ueno
IPC分类号： G09G500
CPC分类号： G06F9/30014
摘要： An internal memory section is divided into plural memory blocks. During a period of time, a relevant memory block of the internal memory section is connected to an external memory unit, while another memory block thereof is connected to a data holding section. During a succeeding period of time, the relevant memory block is connected to the data holding section, while the other memory block is connected to the external memory unit. Data exchange between the data holding section and the external memory unit via the internal memory section is performed while the alternative connection is repeated.
摘要翻译：内部存储部分被分成多个存储块。在一段时间内，内部存储器部分的相关存储器块连接到外部存储器单元，而另一个存储器块连接到数据保持部分。在接下来的一段时间内，相关的存储块连接到数据保持部分，而另一个存储块连接到外部存储器单元。在重复替代连接的同时，经由内部存储器部分执行数据保持部分和外部存储器单元之间的数据交换。

44. 发明授权

US06209126B1 Stall detecting apparatus, stall detecting method, and medium containing stall detecting program 失效
标题翻译：失速检测装置，失速检测方法和包含失速检测程序的介质
公开(公告)号：US06209126B1
公开(公告)日：2001-03-27
申请号：US09141342
申请日：1998-08-27
申请人： Yoko Sasaki , Atsushi Kunimatsu
发明人： Yoko Sasaki , Atsushi Kunimatsu
IPC分类号： G06F945
CPC分类号： G06F11/3664 , G06F11/323 , G06F11/3624
摘要： A stall detecting apparatus and a stall detecting method reduce labor and time to develop a program. The apparatus has an input portion for reading a source program, an interpreter for interpreting the read source program according to processor specifications, an instruction developing unit for developing the interpreted source program into states in pipeline stages of pipeline processing, and a stall detector for detecting stalls in the pipeline processing according to the states of the source program developed in the pipeline stages and providing stall information representing the detected stalls. The stall detecting method realizes these functions of the stall detecting apparatus. The method and apparatus statically analyze a given source program while the source program is being coded and efficiently detect stalls to occur in the source program. The method and apparatus display the stall information together with the source program and a pipeline image of the pipeline processing of the source program.
摘要翻译：失速检测装置和失速检测方法减少了开发程序的人力和时间。该装置具有用于读取源程序的输入部分，用于根据处理器规格解释读取源程序的解释器，用于开发程序的指令显影单元解码源程序转换成流水线处理的流水线阶段的状态，以及停止检测器，用于根据在流水线级中开发的源程序的状态检测流水线处理中的停顿，并提供表示检测到的档位的失速信息。失速检测方法实现失速检测装置的这些功能。该方法和装置在源程序被编码时静态分析给定的源程序，并有效地检测在源程序中发生的停顿。该方法和装置与源程序一起显示失速信息和源程序的流水线处理的流水线图像。

45. 发明授权

US5909588A Processor architecture with divisional signal in instruction decode for parallel storing of variable bit-width results in separate memory locations 失效
标题翻译：具有指令解码分割信号的处理器架构，用于并行存储可变位宽结果，分离存储位置
公开(公告)号：US5909588A
公开(公告)日：1999-06-01
申请号：US671619
申请日：1996-06-28
申请人： Hiroki Fujimura , Hiroyuki Takai , Toshiyuki Yaguchi , Seiji Koino , Mikio Takasugi , Atsushi Kunimatsu
发明人： Hiroki Fujimura , Hiroyuki Takai , Toshiyuki Yaguchi , Seiji Koino , Mikio Takasugi , Atsushi Kunimatsu
IPC分类号： G06F9/30 , G06F9/302 , G06F9/312 , G06F9/34 , G06F9/38 , G06F12/04 , G06F9/345
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30043 , G06F9/3824
摘要： An instruction code is received by an instruction input section 103 and then decoded by the instruction decode section 105 to generate an operand and control signals. The instruction division control section 109 generates a division control signal based on the control signals and an operand selection section 107 generates an operand having a desired bit width by using the operand from the instruction decode section 105 based on the division control signal. An arithmetic section 111 divides the operand into a desired bit width parts based on the division control signal and performs arithmetic operation. A memory access control section 115 receives calculated address and transfers this calculated address and the division control signal to a memory. The memory access control section 115 receives data from the memory and transfers the data into the arithmetic result store section 113.
摘要翻译：指令代码由指令输入部103接收，然后由指令解码部105解码，生成操作数和控制信号。指令分割控制部分109基于控制信号产生除法控制信号，并且操作数选择部分107基于分割控制信号通过使用来自指令解码部分105的操作数来产生具有期望比特宽度的操作数。运算部111基于分割控制信号将运算部分分成所需的位宽部分，进行算术运算。存储器访问控制部分115接收计算的地址并将该计算的地址和分割控制信号传送到存储器。存储器访问控制部分115从存储器接收数据并将数据传送到算术结果存储部分113。

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