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41. 发明授权

US07227789B2 Method and apparatus for filtering output data 有权
标题翻译：用于过滤输出数据的方法和装置
公开(公告)号：US07227789B2
公开(公告)日：2007-06-05
申请号：US11127526
申请日：2005-05-12
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/02 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/22 , G11C2207/2281
摘要： Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a reduced speed penalty. The filtering is selectable by a fuse option.
摘要翻译：用自适应滤波电路滤波杂散输出转换的装置和方法，该自适应滤波电路以降低的速度损失跟踪存储器架构和形状因子。滤波可由保险丝选项选择。

42. 发明授权

US08004892B2 Single latch data circuit in a multiple level cell non-volatile memory device 有权
标题翻译：单级锁存数据电路在多级单元非易失性存储器件中
公开(公告)号：US08004892B2
公开(公告)日：2011-08-23
申请号：US12632121
申请日：2009-12-07
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C11/34
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2211/5642 , G11C2211/5647
摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.
摘要翻译：单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。该电路由具有反向节点和非反相节点的锁存器组成。第一控制晶体管选择性地将非反相节点耦合到锁存器输出。第二控制晶体管选择性地将反相节点耦合到锁存器输出。复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

43. 发明申请

US20100085807A1 SINGLE LATCH DATA CIRCUIT IN A MULTIPLE LEVEL CELL NON-VOLATILE MEMORY DEVICE 有权
标题翻译：多级单元存储器中的单锁数据电路
公开(公告)号：US20100085807A1
公开(公告)日：2010-04-08
申请号：US12632121
申请日：2009-12-07
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C16/04 , G11C7/10 , G11C16/06
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2211/5642 , G11C2211/5647
摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.
摘要翻译：单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。该电路由具有反向节点和非反相节点的锁存器组成。第一控制晶体管选择性地将非反相节点耦合到锁存器输出。第二控制晶体管选择性地将反相节点耦合到锁存器输出。复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

44. 发明授权

US07466602B2 Method and apparatus for filtering output data 有权
标题翻译：用于过滤输出数据的方法和装置
公开(公告)号：US07466602B2
公开(公告)日：2008-12-16
申请号：US11758373
申请日：2007-06-05
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/02 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/22 , G11C2207/2281
摘要： Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a reduced speed penalty. The filtering is selectable by a fuse option.
摘要翻译：用自适应滤波电路滤波杂散输出转换的装置和方法，该自适应滤波电路以降低的速度损失跟踪存储器架构和形状因子。滤波可由保险丝选项选择。

45. 发明申请

US20080266953A1 SINGLE LATCH DATA CIRCUIT IN A MULTIPLE LEVEL CELL NON-VOLATILE MEMORY DEVICE 有权
标题翻译：多级单元存储器中的单锁数据电路
公开(公告)号：US20080266953A1
公开(公告)日：2008-10-30
申请号：US12170563
申请日：2008-07-10
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C7/10 , G11C16/04
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2211/5642 , G11C2211/5647
摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.
摘要翻译：单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。该电路由具有反向节点和非反相节点的锁存器组成。第一控制晶体管选择性地将非反相节点耦合到锁存器输出。第二控制晶体管选择性地将反相节点耦合到锁存器输出。复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

46. 发明申请

US20070189071A1 Single latch data circuit in a multiple level cell non-volatile memory device 有权
标题翻译：单级锁存数据电路在多级单元非易失性存储器件中
公开(公告)号：US20070189071A1
公开(公告)日：2007-08-16
申请号：US11506428
申请日：2006-08-18
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C14/00 , G11C16/04 , G11C7/10 , G11C11/34
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2211/5642 , G11C2211/5647
摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.
摘要翻译：单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。该电路由具有反向节点和非反相节点的锁存器组成。第一控制晶体管选择性地将非反相节点耦合到锁存器输出。第二控制晶体管选择性地将反相节点耦合到锁存器输出。复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

47. 发明申请

US20130272071A1 DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS 有权
标题翻译：确定记忆细胞组合的软数据
公开(公告)号：US20130272071A1
公开(公告)日：2013-10-17
申请号：US13444443
申请日：2012-04-11
申请人： Violante Moschiano , Tommaso Vali , Mark A. Hawes
发明人： Violante Moschiano , Tommaso Vali , Mark A. Hawes
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/26
摘要： The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and a second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells.
摘要翻译：本公开包括用于确定存储器单元的组合的软数据的装置和方法。多个实施例包括存储单元的阵列，其包括第一和第二存储单元，每个第一和第二存储器单元可编程为多个程序状态之一，其中第一和第二存储器单元的编程状态的组合对应于多个数据状态，以及耦合到阵列并被配置为确定与第一和第二存储器单元的程序状态相关联的软数据的缓冲器和/或控制器以及与对应于程序状态的组合的数据状态相关联的软数据至少部分地基于与第一和第二存储器单元的程序状态相关联的软数据。

48. 发明授权

US09087594B2 Memory apparatus, systems, and methods 有权
标题翻译：内存设备，系统和方法
公开(公告)号：US09087594B2
公开(公告)日：2015-07-21
申请号：US13563314
申请日：2012-07-31
申请人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
发明人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
IPC分类号： G11C11/34 , G11C16/04 , G11C16/26 , G11C11/56 , G11C16/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2211/5641
摘要： Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.
摘要翻译：电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。对于相邻编程的侵略存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。提供附加的装置，系统和方法。

49. 发明授权

US09030870B2 Threshold voltage compensation in a multilevel memory 有权
标题翻译：多电平存储器中的阈值电压补偿
公开(公告)号：US09030870B2
公开(公告)日：2015-05-12
申请号：US13219439
申请日：2011-08-26
申请人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
发明人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
IPC分类号： G11C11/34 , G11C16/04 , G11C16/26 , G11C11/56 , G11C16/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2211/5641
摘要： Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.
摘要翻译：电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。相邻编程的“侵略者”存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。

50. 发明授权

US08681562B2 Memories and methods of programming memories 有权
标题翻译：记忆和程序记忆的方法
公开(公告)号：US08681562B2
公开(公告)日：2014-03-25
申请号：US13051599
申请日：2011-03-18
申请人： Pranav Kalavade , Akira Goda , Tommaso Vali , Violante Moschiano
发明人： Pranav Kalavade , Akira Goda , Tommaso Vali , Violante Moschiano
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C16/3459
摘要： Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of the threshold voltage distribution.
摘要翻译：公开了用于调整存储器上部页面编程的装置和方法。在至少一个实施例中，在用于较低页编程的单个编程脉冲之后确定阈值电压分布上限，并且基于所确定的阈值电压分布的上限来调整上页编程开始电压。

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