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41. 发明授权

US06349059B1 Method for reading data from a non-volatile memory device with autodetect burst mode reading and corresponding reading circuit 失效
标题翻译：从具有自动检测突发模式读取的非易失性存储器件读取数据的方法和相应的读取电路
公开(公告)号：US06349059B1
公开(公告)日：2002-02-19
申请号：US09716746
申请日：2000-11-20
申请人： Simone Bartoli , Antonio Geraci , Mauro Sali , Lorenzo Bedarida
发明人： Simone Bartoli , Antonio Geraci , Mauro Sali , Lorenzo Bedarida
IPC分类号： G11C1604
CPC分类号： G11C7/1033 , G11C7/1045 , G11C7/1072
摘要： A method for reading data from an integrated electronic memory device including a non-volatile memory matrix includes supplying the memory with an address of a memory location where a reading is to be effected, accessing the memory matrix in a random read mode, supplying the memory with a clock signal and an address acknowledge signal (LAN), detecting a request for burst read mode access, and starting the burst reading as the clock signal shows a rising edge. A related circuit is also provided.
摘要翻译：一种用于从包括非易失性存储器矩阵的集成电子存储器件读取数据的方法包括向存储器提供要进行读取的存储器位置的地址，以随机读取模式访问存储器矩阵，提供存储器具有时钟信号和地址确认信号（LAN），检测对突发读取模式存取的请求，以及当时钟信号显示上升沿时启动突发读取。还提供了相关的电路。

42. 发明授权

US06320361B2 Buffer device with dual supply voltage for low supply voltage applications 失效
标题翻译：用于低电源电压应用的双电源电压缓冲器件
公开(公告)号：US06320361B2
公开(公告)日：2001-11-20
申请号：US09736984
申请日：2000-12-13
申请人： Vincenzo Dima , Lorenzo Bedarida , Antonino Geraci , Simone Bartoli
发明人： Vincenzo Dima , Lorenzo Bedarida , Antonino Geraci , Simone Bartoli
IPC分类号： G05F140
CPC分类号： G05F3/242
摘要： An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.
摘要翻译：一种具有第一和第二电源电压基准的输出缓冲器装置，该第一参考电压值低于第二电压基准。输出缓冲器件包括第一和第二互补MOS晶体管，这些晶体管串联连接在一个电源电压基准和另一个电压基准之间，栅极端子连接在一起并连接到该缓冲器件的输入端，并且具有漏极连接在一起的端子和缓冲器的输出端子。有利地，第一晶体管连接到第一电源电压基准。此外，输出缓冲器件包括与第一MOS晶体管相同类型的至少一个额外的驱动MOS晶体管，并且放置在第二电源电压基准和缓冲器件的输出端之间。

43. 发明授权

US08837252B2 Memory decoder circuit 有权
标题翻译：内存解码电路
公开(公告)号：US08837252B2
公开(公告)日：2014-09-16
申请号：US13485675
申请日：2012-05-31
申请人： Lorenzo Bedarida , Nicolas Zammit , Emmanuel Racape
发明人： Lorenzo Bedarida , Nicolas Zammit , Emmanuel Racape
IPC分类号： G11C11/00
CPC分类号： G11C8/10
摘要： A decoder circuit includes high voltage and low voltage transistors. The decoder circuit uses the high voltage transistors during modify operations to provide a high voltage, e.g., a boosted voltage, to memory cells to change memory cell status or perform other operations. The decoder circuit uses the low voltage transistors during read operations.
摘要翻译：解码器电路包括高压和低压晶体管。解码器电路在修改操作期间使用高压晶体管来向存储器单元提供高电压，例如升压电压，以改变存储器单元状态或执行其他操作。解码器电路在读取操作期间使用低电压晶体管。

44. 发明授权

US07049880B2 High precision digital-to-analog converter with optimized power consumption 有权
标题翻译：具有优化功耗的高精度数模转换器
公开(公告)号：US07049880B2
公开(公告)日：2006-05-23
申请号：US11119675
申请日：2005-05-02
申请人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
发明人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/07 , H03M1/765
摘要： A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.
摘要翻译：一种具有双向切换装置的调节电荷泵电路，其在提供精确和稳定的电压输出的第一反馈通路与从电源提供具有低电流消耗的调节电压输出的第二反馈通路之间切换。第一反馈通道通过调节将电流吸引到电压输出的通过装置来保持精确的电压输出。第二反馈通道通过控制时钟输入到电荷泵的连接来调节电压输出。可变电阻用于设置电压输出的稳定电平。通过使用组合逻辑电路将数字输入信号转换成可变电阻器的控制信号，形成数模转换器。

45. 发明授权

US06567318B2 Control circuit for an output driving stage of an integrated circuit 有权
公开(公告)号：US06567318B2
公开(公告)日：2003-05-20
申请号：US09991493
申请日：2001-11-21
申请人： Lorenzo Bedarida , Luca Vandi , Carlo Lisi , Andrea Bellini
发明人： Lorenzo Bedarida , Luca Vandi , Carlo Lisi , Andrea Bellini
IPC分类号： G11C1604
CPC分类号： G05F3/245
摘要： An impedance control circuit controls the impedance of an integrated output driving stage. The integrated output driving stage includes at least one enabling/disabling transistor and at least one driving transistor. The impedance control circuit includes a variable impedance circuit having an impedance that varies with the temperature in correlation with the impedance of the output driving stage. A control circuit is connected to the variable impedance circuit for generating at least one enabling/disabling signal for the at least one enabling/disabling transistor based upon a control signal correlated to the impedance of the variable impedance circuit. The impedance control circuit also includes a current generating circuit for applying to the variable impedance circuit a current which remains substantially stable as the temperature varies.

46. 发明申请

US20080164948A1 BIASING CURRENT TO SPEED UP CURRENT MIRROR SETTLING TIME 有权
标题翻译：偏移电流以加快电流反射时间
公开(公告)号：US20080164948A1
公开(公告)日：2008-07-10
申请号：US11619729
申请日：2007-01-04
申请人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Andrea Bettini
发明人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Andrea Bettini
IPC分类号： H03F3/04
CPC分类号： H03F3/343 , G09G3/20 , G09G3/3216 , G09G3/3225
摘要： A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.
摘要翻译：电流镜电路包括耦合到第二电流镜晶体管的第一电流镜晶体管。负载耦合到第二电流镜晶体管。第一电流源耦合到第一电流镜晶体管以引起偏置电流流过第一电流镜晶体管，并且第二电流源耦合到第二电流镜晶体管并且与负载并联以分流偏置电流远离负载。

47. 发明申请

US20050189983A1 High precision digital-to-analog converter with optimized power consumption 有权
公开(公告)号：US20050189983A1
公开(公告)日：2005-09-01
申请号：US11119675
申请日：2005-05-02
申请人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
发明人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
IPC分类号： G05F1/10 , G05F3/02 , H02M20060101 , H02M3/07 , H02M5/42 , H03M1/76
CPC分类号： H02M3/07 , H03M1/765
摘要： A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.

48. 发明授权

US5793676A Nonvolatile memory device having sectors of selectable size and number 失效
公开(公告)号：US5793676A
公开(公告)日：1998-08-11
申请号：US649857
申请日：1996-05-03
申请人： Lorenzo Bedarida , Giovanni Campardo , Giuseppe Fusillo , Andrea Silvagni
发明人： Lorenzo Bedarida , Giovanni Campardo , Giuseppe Fusillo , Andrea Silvagni
IPC分类号： G11C8/12 , G11C16/08 , G11C11/34
CPC分类号： G11C8/12 , G11C16/08
摘要： A memory array is divided, at the design stage, into a plurality of elementary sectors; depending on the specific application and the requirements of the user, the elementary sectors are grouped into composite sectors of desired size and number; a correlating unit memorizes the correlation between each composite sector and the elementary sectors; and, to address a composite sector, the relative address is supplied to the correlating unit which provides for addressing the elementary sectors associated with the addressed composite sector on the basis of the memorized correlation table.

49. 发明申请

US20130322185A1 Memory Decoder Circuit 有权
标题翻译：存储器解码器电路
公开(公告)号：US20130322185A1
公开(公告)日：2013-12-05
申请号：US13485675
申请日：2012-05-31
申请人： Lorenzo Bedarida , Nicolas Zammit , Emmanuel Racape
发明人： Lorenzo Bedarida , Nicolas Zammit , Emmanuel Racape
IPC分类号： G11C5/14
CPC分类号： G11C8/10
摘要： A decoder circuit includes high voltage and low voltage transistors. The decoder circuit uses the high voltage transistors during modify operations to provide a high voltage, e.g., a boosted voltage, to memory cells to change memory cell status or perform other operations. The decoder circuit uses the low voltage transistors during read operations.
摘要翻译：解码器电路包括高压和低压晶体管。解码器电路在修改操作期间使用高电压晶体管来向存储器单元提供高电压，例如升压电压，以改变存储器单元状态或执行其他操作。解码器电路在读取操作期间使用低电压晶体管。

50. 发明申请

US20050073355A1 HIGH PRECISION DIGITAL-TO-ANALOG CONVERTER WITH OPTIMIZED POWER CONSUMPTION 有权
标题翻译：具有优化功耗的高精度数字到模拟转换器
公开(公告)号：US20050073355A1
公开(公告)日：2005-04-07
申请号：US10753273
申请日：2004-01-07
申请人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
发明人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
IPC分类号： G05F1/10 , G05F3/02 , H02M20060101 , H02M3/07 , H02M5/42 , H03M1/76
CPC分类号： H02M3/07 , H03M1/765
摘要： A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.
摘要翻译：一种具有双向切换装置的调节电荷泵电路，其在提供精确和稳定的电压输出的第一反馈通路与从电源提供具有低电流消耗的调节电压输出的第二反馈通路之间切换。第一反馈通道通过调节将电流吸引到电压输出的通过装置来保持精确的电压输出。第二反馈通道通过控制时钟输入到电荷泵的连接来调节电压输出。可变电阻用于设置电压输出的稳定电平。通过使用组合逻辑电路将数字输入信号转换成可变电阻器的控制信号，形成数模转换器。

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