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41. 发明授权

US07098834B2 Multi-mode analog to digital converter 失效
标题翻译：多模式模数转换器
公开(公告)号：US07098834B2
公开(公告)日：2006-08-29
申请号：US10969283
申请日：2004-10-20
申请人： Lloyd F. Linder , Michael F. Clingempeel , William W. Cheng , William J. Rinard , Benjamin Felder
发明人： Lloyd F. Linder , Michael F. Clingempeel , William W. Cheng , William J. Rinard , Benjamin Felder
IPC分类号： H03M1/12 , H03M3/00 , H03M1/44
CPC分类号： H03M1/007 , H03M1/167
摘要： A multi-mode analog to, digital converter (ADC). The novel ADC includes an input terminal for receiving an analog input signal; a plurality of processing stages, each processing stage adapted to generate an output signal from an input to that processing stage; and a mechanism for determining a mode of operation and in accordance therewith connect the processing stages and the input terminal in a predetermined configuration. In an illustrative embodiment, the ADC can be configured as a subranging ADC, and the mechanism for determining, the mode of operation includes a signal processor for automatically selecting the mode of operation based on the frequency components of the input signal.
摘要翻译：多模式模数转换器（ADC）。该新型ADC包括用于接收模拟输入信号的输入端; 多个处理级，每个处理级适于从输入到该处理级产生输出信号; 以及用于确定操作模式并根据其以预定配置连接处理级和输入端的机构。在说明性实施例中，ADC可以被配置为子泛化ADC，并且用于确定操作模式的机制包括用于基于输入信号的频率分量自动选择操作模式的信号处理器。

42. 发明授权

US07098684B2 High speed switch 有权
标题翻译：高速开关
公开(公告)号：US07098684B2
公开(公告)日：2006-08-29
申请号：US10740173
申请日：2003-12-18
申请人： Don C. Devendorf , Seth L. Everton , Lloyd F. Linder , Michael H. Liou
发明人： Don C. Devendorf , Seth L. Everton , Lloyd F. Linder , Michael H. Liou
IPC分类号： H03K19/013
CPC分类号： G11C27/02 , H03K17/04113
摘要： A high speed switch. The novel switch includes an input circuit having a transistor Q1 for receiving an input signal, a first mechanism for providing a path from an output of Q1 to an output terminal, and a second mechanism for receiving a control signal and in accordance therewith reducing the conductivity of the path during a mute mode. The first mechanism includes a first circuit for providing a first path from an output of Q1 to a first node, and a second circuit for providing a second path connecting the first node to the output terminal. The second mechanism is adapted to apply a signal to the first node during the mute mode such that the first and second circuits are off or partially conducting. The switch also includes a circuit for clamping the first node to a first predetermined voltage during the mute mode.
摘要翻译：高速开关新型开关包括具有用于接收输入信号的晶体管Q 1的输入电路，用于提供从Q 1的输出到输出端的路径的第一机构，以及用于接收控制信号的第二机构，并且根据其减少在静音模式下路径的电导率。第一机构包括用于提供从Q1的输出到第一节点的第一路径的第一电路和用于提供将第一节点连接到输出端子的第二路径的第二电路。第二机构适于在静音模式期间将信号施加到第一节点，使得第一和第二电路关闭或部分导通。开关还包括用于在静音模式期间将第一节点钳位到第一预定电压的电路。

43. 发明授权

US07095347B2 Digitally trimmed DAC cell 有权
标题翻译：数字修整DAC电池
公开(公告)号：US07095347B2
公开(公告)日：2006-08-22
申请号：US10715262
申请日：2003-11-17
申请人： Erick M. Hirata , Roger N. Kosaka , Christopher B. Langit , Lloyd F. Linder
发明人： Erick M. Hirata , Roger N. Kosaka , Christopher B. Langit , Lloyd F. Linder
IPC分类号： H03M1/66
CPC分类号： G05F3/22
摘要： A digitally trimmed current source. The novel current source includes a first circuit for generating a current in response to an applied voltage and a resistance variable in response to a control signal, and a second circuit for supplying the control signal. The first circuit includes a resistive network comprised of a plurality of resistors; a plurality of switches, each switch coupled to one of the resistors and adapted to selectively switch the resistor in and out of the resistive network in response to the control signal; and a transistor adapted to apply a voltage across the resistive network to generate a current.
摘要翻译：数字修剪电流源。新颖的电流源包括响应于施加的电压产生电流的第一电路和响应于控制信号的电阻变量，以及用于提供控制信号的第二电路。第一电路包括由多个电阻组成的电阻网络; 多个开关，每个开关耦合到所述电阻器之一并且适于响应于所述控制信号选择性地将所述电阻器进入和流出所述电阻网络; 以及适于在电阻网络上施加电压以产生电流的晶体管。

44. 发明授权

US06882294B2 Resistive ladder, summing node circuit, and trimming method for a subranging analog to digital converter 失效
标题翻译：电阻式梯形图，求和节点电路，以及用于子模拟数字转换器的修整方法
公开(公告)号：US06882294B2
公开(公告)日：2005-04-19
申请号：US10635826
申请日：2003-08-06
申请人： Lloyd F. Linder , Benjamin Felder
发明人： Lloyd F. Linder , Benjamin Felder
IPC分类号： H03M1/06 , H03M1/10 , H03M1/16 , H03M1/36 , H03M1/74 , H03M1/78
CPC分类号： H03M1/0682 , H03M1/1057 , H03M1/167 , H03M1/363 , H03M1/747
摘要： A subranging analog to digital converter (ADC). The ADC (200) includes a novel resistive ladder (56) for a differential quantizer (50) and a novel summing node circuit (150). The novel resistive ladder (56) includes an input terminal (52), a plurality of serially connected resistors R coupled to the input terminal (52), and a pair of complementary current sources (66 and 68) for maintaining a constant current flow through the ladder (56). The novel summing node circuit (150) includes an input terminal (152) for receiving an input signal, a pair of complementary DACs (156 and 158) for generating a reconstruction signal, and a summing amplifier (164) for subtracting the reconstruction signal from the input signal to produce a residue signal.The invention also includes a method for trimming the subranging ADC. The novel method (250) includes the steps of trimming the complementary current sources of the coarse quantizer to match each other (252), trimming each of the DAC cells on one of the complementary DACs (254), trimming the overall DAC gain to match the gain of the coarse quantizer (256); and trimming the gain of the fine quantizer to match one coarse quantization Q level (260).
摘要翻译：一个子模块转换器（ADC）。 ADC（200）包括用于差分量化器（50）和新颖求和节点电路（150）的新型电阻梯（56）。新型电阻梯（56）包括输入端（52），耦合到输入端（52）的多个串联的电阻R和一对互补电流源（66和68），用于保持恒定的电流流通梯子（56）。所述新型求和节点电路（150）包括用于接收输入信号的输入端（152），用于产生重构信号的一对互补DAC（156和158），以及用于从输入信号产生残留信号。本发明还包括一种用于修整Subranging ADC的方法。新颖的方法（250）包括以下步骤：对粗量化器的互补电流源进行微调以彼此匹配（252），修整其中一个互补DAC（254）上的每个DAC单元，修整总体DAC增益以匹配粗量化器（256）的增益; 并调整精细量化器的增益以匹配一个粗量化Q级（260）。

45. 发明授权

US06693980B1 Wideband fast-hopping receiver front-end and mixing method 有权
标题翻译：宽带快跳接收机前端和混合方式
公开(公告)号：US06693980B1
公开(公告)日：2004-02-17
申请号：US09664298
申请日：2000-09-18
申请人： Lloyd F. Linder , Don C. Devendorf
发明人： Lloyd F. Linder , Don C. Devendorf
IPC分类号： H04L2722
CPC分类号： H03D7/165
摘要： A wideband fast-hopping receiver front-end uses direct digital synthesis (DDS) to provide quadrature LO signals to the front-end's mixers. A DDS circuit stores multiple digital word sequences which represent desired waveforms, and outputs desired sequence pairs to a pair of DACs in response to a clock signal and a command signal. The DACs convert the sequences to analog signals, which are filtered and squared as necessary to provide quadrature LO signals to the mixers. Frequency hopping is accomplished by changing the command signal, which causes a different pair of sequences to be output and the frequency of the LO signals provided to the mixers to be changed. Active image rejection is combined with DDS LO generation to provide faster frequency hopping. The front-end is combined with an ADC and a communications signal processor to provide a complete system, all of which can be integrated together on a common substrate.
摘要翻译：宽带快速跳频接收机前端使用直接数字合成（DDS）向前端的混频器提供正交LO信号。 DDS电路存储表示所需波形的多个数字字序列，并响应于时钟信号和命令信号将期望的序列对输出到一对DAC。 DAC将序列转换为模拟信号，根据需要进行滤波和平方以向混频器提供正交LO信号。通过改变命令信号来实现跳频，这导致输出不同的序列对，并且提供给混频器的LO信号的频率被改变。主动图像抑制与DDS LO生成相结合，提供更快的跳频。前端与ADC和通信信号处理器相结合，提供一个完整的系统，所有系统都可以集成在一个共同的基板上。

46. 发明授权

US5859558A Low voltage analog front end 失效
标题翻译：低压模拟前端
公开(公告)号：US5859558A
公开(公告)日：1999-01-12
申请号：US827855
申请日：1997-04-11
申请人： Ricky Y. Chen , Lloyd F. Linder , Don C. Devendorf
发明人： Ricky Y. Chen , Lloyd F. Linder , Don C. Devendorf
IPC分类号： H03D7/14 , H03F3/343 , H03F3/45 , G06G7/12
CPC分类号： H03F3/45071 , H03D7/1408 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03F3/343 , H03D2200/0033 , H03D2200/0043
摘要： A low voltage analog front end (AFE) includes a differential transistor pair which converts an input voltage, typically A.C.-coupled to the pair's control inputs, to a differential current. Impedance networks connected to each transistor's control input are joined together at a common node, and a current source is connected to the node which causes DC bias currents to be mirrored through the pair's current circuits, so that the AFE's differential output current comprises a differential current produced by the pair in response to an input voltage and superimposed on the DC bias currents. The current source preferably generates mirrored currents which are larger than its reference current to linearize the pair's response and to provide the AFE with a wide dynamic range. An input to the AFE sees a low impedance which is about equal to the sum of the impedance networks, which can be resistive or complex as needed. The AFE has widespread application as a front end circuit, serving as a low voltage input stage for a Gilbert mixer, for example. By generating bias currents via the pair's control inputs, supply voltage headroom requirements are reduced, improving a system's dynamic range and/or enabling the use of lower voltage power supplies. The AFE can be configured as either a differential or single-ended voltage-to-differential current converter.
摘要翻译：低电压模拟前端（AFE）包括差分晶体管对，其将输入电压（通常与耦合到对的控制输入的交流耦合）转换为差分电流。连接到每个晶体管的控制输入的阻抗网络在公共节点处连接在一起，并且电流源连接到节点，其导致DC偏置电流通过该对电流电路被镜像，使得AFE的差分输出电流包括差分电流由输出电压响应输入电压产生并叠加在直流偏置电流上。电流源优选地产生大于其参考电流的镜像电流，以使对的响应线性化并为AFE提供宽的动态范围。 AFE的输入端看到一个低阻抗，大约等于阻抗网络的总和，根据需要可以阻抗或复杂。 AFE作为前端电路广泛应用，例如用作Gilbert混频器的低电压输入级。通过经由该对的控制输入产生偏置电流，降低了电源电压余量要求，提高系统的动态范围和/或使能低电压电源。 AFE可以配置为差分或单端电压 - 差分电流转换器。

47. 发明授权

US09813030B1 Wideband single-ended IM3 distortion nulling 有权
公开(公告)号：US09813030B1
公开(公告)日：2017-11-07
申请号：US15201206
申请日：2016-07-01
申请人： Wais M. Ali , Lloyd F. Linder
发明人： Wais M. Ali , Lloyd F. Linder
IPC分类号： H03F1/22 , H03F1/32 , H03F3/195 , H03F1/26
CPC分类号： H03F1/3205 , H03F1/223 , H03F1/26 , H03F1/3223 , H03F3/195 , H03F2200/411 , H03F2200/451 , H03F2201/3212
摘要： System-on-chip (SOC) products using high frequency, wideband, highly linear, CMOS and BiCMOS processes will be the next evolution of wireless and wireline communications integrated circuits. Aspects described herein can provide enhanced overall performance over existing prior art single-ended, wideband RF amplifier topologies. A single-ended third order intermodulation distortion nulling circuit can extend the dynamic range for wideband amplifiers up to an order-of-magnitude, without a DC power or noise figure (NF) penalty. The application of distortion nulling can be extended to all the building blocks used in CMOS/BiCMOS RF transceivers to improve performance. The application of this concept to all of the building blocks in an RF transceiver will allow the dynamic range of the transceiver to be increased without suffering a DC power dissipation increase or a significant noise increase.

48. 发明授权

US06975189B1 On-chip multilayer metal shielded transmission line 有权
标题翻译：片上多层金属屏蔽传输线
公开(公告)号：US06975189B1
公开(公告)日：2005-12-13
申请号：US09705134
申请日：2000-11-02
申请人： Alan E. Reamon , Lloyd F. Linder , Erick M. Hirata , Nick Elmi
发明人： Alan E. Reamon , Lloyd F. Linder , Erick M. Hirata , Nick Elmi
IPC分类号： H01L23/522 , H01L23/552 , H01P3/08
CPC分类号： H01P3/088 , H01L23/5225 , H01L23/552 , H01L2223/6622 , H01L2924/0002 , H01L2924/00
摘要： Multi-layer metal-shielded monolithic transmission lines are formed in side-by-side arrangement by depositing parallel planar thin film, conductive layers, separated by nonconductive separator layers to form a stack of alternating conductive and nonconductive layers. The conductive layers form a top and a bottom conductive plane and establish a mutually registered selected width of the stack. A center conductive layer has laterally spaced apart conductive strips separated by nonconductive spacer layers. The two laterally terminal of the conductive strips are spaced at the selected width. Each of the nonconductive separator layers provides a plurality of elongated vias between the two lateral terminals of the three conductive strips and the conductive planes. The vias are filled as each next metal deposition is applied for electrically interconnecting the conductive strips and planes so as to form a monolithic conductive shield about the centermost signal carrying conductor of the three conductive strips, providing electrical isolation in a coaxial arrangement.
摘要翻译：多层金属屏蔽单片传输线通过沉积由非导电隔离层隔开的平行平面薄膜，导电层形成并排布置，以形成交替的导电和非导电层的堆叠。导电层形成顶部和底部的导电平面并且建立堆叠的相互注册的选定宽度。中心导电层具有由非导电间隔层隔开的横向隔开的导电条。导电条的两个横向端子以选定的宽度间隔开。每个非导电隔离层在三个导电条和导电平面的两个侧向端之间提供多个细长的通孔。当每个下一次金属沉积被施加以电连接导电条和平面时，通孔被填充，以便围绕三个导电条的中心信号承载导体形成单片导电屏蔽，从而在同轴布置中提供电隔离。

49. 发明授权

US06931083B1 Low noise, low distortion, muxable Gilbert mixer signal processing system and method with AGC functionality 有权
标题翻译：低噪声，低失真，可混合的吉尔伯特混频器信号处理系统和具有AGC功能的方法
公开(公告)号：US06931083B1
公开(公告)日：2005-08-16
申请号：US09579596
申请日：2000-05-26
申请人： Lloyd F. Linder , Clifford N. Duong , Don C. Devendorf
发明人： Lloyd F. Linder , Clifford N. Duong , Don C. Devendorf
IPC分类号： H03D7/00 , H03D7/14 , H04B1/16 , H04B1/26 , H04L27/08
CPC分类号： H03D7/1433 , H03D7/1425 , H03D7/1458 , H03D7/1491
摘要： A signal processing system and method. The inventive system includes a first circuit for distributing an input signal between two or more channels in a current mode of operation. A second circuit is disposed in each of the channels for processing the input signal and providing an output signal in response thereto. A third circuit is provided to combine the signals output by the processing circuit. A fourth circuit is included for controlling the first and the third circuits. In a specific illustrative embodiment, the system further includes a radio frequency stage for downconverting a received signal and providing the input signal in response thereto. In the specific embodiment, the first circuit includes a mixing circuit. The mixing circuit includes Gilbert cells and circuitry for providing automatic gain control for each of the channels individually. The Gilbert cells and the automatic gain control circuitry are driven by a transconductance amplifier and therefore operate in a current mode. Differential digital automatic gain control signals are provided in response to a channel select signal from a digital control circuit. The inventive circuit provides multiple IF channels which may be filtered individually. The invention thereby provides wide band operation in a simple, single stage implementation that consumes little power. Further, the current mode thereof is effective in the reduction of insertion loss.
摘要翻译：信号处理系统及方法。本发明的系统包括用于在当前操作模式中在两个或更多个通道之间分配输入信号的第一电路。在每个通道中设置第二电路以处理输入信号并响应于此提供输出信号。提供第三电路以组合由处理电路输出的信号。包括用于控制第一和第三电路的第四电路。在具体的说明性实施例中，该系统还包括用于下变频接收信号并响应于此提供输入信号的射频级。在具体实施例中，第一电路包括混合电路。混合电路包括吉尔伯特单元和用于单独为每个通道提供自动增益控制的电路。吉尔伯特单元和自动增益控制电路由跨导放大器驱动，因此在当前模式下工作。响应于来自数字控制电路的通道选择信号提供差分数字自动增益控制信号。本发明的电路提供可以单独过滤的多个IF信道。因此，本发明在消耗很少功率的简单的单级实现中提供宽带操作。此外，其电流模式在减少插入损耗方面是有效的。

50. 发明授权

US06891424B1 Monolithic payload IF switch 失效
标题翻译：单片载荷中频开关
公开(公告)号：US06891424B1
公开(公告)日：2005-05-10
申请号：US09408114
申请日：1999-09-29
申请人： Erick M. Hirata , Lloyd F. Linder
发明人： Erick M. Hirata , Lloyd F. Linder
IPC分类号： H04B7/185 , H04Q3/52 , H03K17/62
CPC分类号： H04Q3/521 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/1319 , H04Q2213/1332 , H04Q2213/13322
摘要： A crosspoint switch architecture (10). The inventive architecture (10) includes a monolithic substrate (11) on which a plurality (N) of electrical inputs are provided. In addition, a plurality (M) of electrical outputs are provided on the substrate (11). A switch is disposed on the substrate (11) for selectively interconnecting the inputs to the outputs and a control circuit (16) is disposed on the substrate (11) for controlling the switch. The switch comprises M, N to 1, multiplexers (14), each multiplexer (14) being adapted to receive each of the N electrical inputs. In the illustrative embodiment, each of the N inputs to each of the multiplexers is received through a respective one of N switchable amplifiers (18). The output of each amplifier (18) is provided to a respective one of N switchable isolation buffers (19). The outputs of the buffers (19) are summed and buffered to provide the output of each multiplexer (14). The control circuit (16) selects which input is to be passed through to the output of a given multiplexer (14). In the illustrative embodiment, the control circuit (16) includes a serial in, parallel out shift register and decode logic circuitry.
摘要翻译：交叉点交换架构（10）。本发明的架构（10）包括其上提供有多个（N个）电输入的单片基板（11）。另外，在基板（11）上设置有多个（M）的电输出。开关设置在基板（11）上，用于将输入选择性地互连到输出端，并且控制电路（16）设置在基板（11）上用于控制开关。开关包括M，N至1，多路复用器（14），每个多路复用器（14）适于接收N个电输入中的每一个。在说明性实施例中，通过N个可切换放大器（18）中的相应一个接收每个多路复用器的N个输入中的每一个。每个放大器（18）的输出被提供给N个可切换隔离缓冲器（19）中的相应一个。缓冲器（19）的输出被相加和缓冲以提供每个多路复用器（14）的输出。控制电路（16）选择哪个输入要传递给给定多路复用器（14）的输出端。在说明性实施例中，控制电路（16）包括串行，并行输出移位寄存器和解码逻辑电路。

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