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41. 发明授权

US08775977B2 Decomposition and marking of semiconductor device design layout in double patterning lithography 有权
标题翻译：半双工图案平版印刷中半导体器件设计布局的分解和标记
公开(公告)号：US08775977B2
公开(公告)日：2014-07-08
申请号：US13027520
申请日：2011-02-15
申请人： Chin-Chang Hsu , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng , Lee-Chung Lu
发明人： Chin-Chang Hsu , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F7/70433 , G03F7/70466
摘要： Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.
摘要翻译：提供了一种用于评估半导体器件级的设计布局并通过分解设计布局来确定和指定由不同光掩模形成的设计布局的不同特征的系统和方法。这些特征由标记指定，该标记将各种器件特征与将在其上形成的多个光掩模相关联，然后使用双重图案化光刻DPL技术在半导体器件层面上产生。标记是在设备级完成的，并被包括在由设计公司提供给光掩模铸造厂的电子文件中。除了正在分解的设计布局的重叠和关键维度考虑之外，在确定和标记各种设备时，还考虑了各种其他设备标准，设计标准处理标准及其相关性以及设备环境和其他设备层特征。

42. 发明授权

US08119310B1 Mask-shift-aware RC extraction for double patterning design 有权
标题翻译：面罩移位感知RC提取双图案设计
公开(公告)号：US08119310B1
公开(公告)日：2012-02-21
申请号：US12872938
申请日：2010-08-31
申请人： Lee-Chung Lu , Yi-Kan Cheng , Hsiao-Shu Chao , Ke-Ying Su , Cheng-Hung Yeh , Dian-Hau Chen , Ru-Gun Liu , Wen-Chun Huang
发明人： Lee-Chung Lu , Yi-Kan Cheng , Hsiao-Shu Chao , Ke-Ying Su , Cheng-Hung Yeh , Dian-Hau Chen , Ru-Gun Liu , Wen-Chun Huang
IPC分类号： G03F9/00 , G06F17/50
CPC分类号： G03F1/70
摘要： A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.
摘要翻译：一种方法包括提供集成电路设计的布局，以及从布局生成多个双重图案化分解，多个双重图案化分解中的每一个包括分离到第一掩模的图案和双图案掩模组的第二掩模。确定第一和第二掩模之间的最大偏移，其中最大偏移是用于在晶片上实现布局的制造过程中的最大预期掩模移位。对于多个双重图案化分解中的每一个，使用由最大偏移限定的范围内的掩模移位来模拟最坏情况的性能值。

43. 发明申请

US20110035717A1 Design Optimization for Circuit Migration 有权
标题翻译：电路迁移的设计优化
公开(公告)号：US20110035717A1
公开(公告)日：2011-02-10
申请号：US12846594
申请日：2010-07-29
申请人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu Alex Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
发明人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu Alex Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5068 , G06F17/5072
摘要： An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.
摘要翻译：本发明的实施例是一种用于提供集成电路布局的经调整的电子表示的计算机程序产品。计算机程序产品具有其上体现计算机程序的介质。此外，计算机程序包括用于从完整节点网表提供全节点单元的计算机程序代码，用于缩放全节点单元以提供收缩节点单元的计算机程序代码，用于提供全节点单元的定时性能的计算机程序代码和收缩节点单元，用于将全节点单元的定时性能与收缩节点单元的定时性能进行比较的计算机程序代码以及用于提供第一网表的计算机程序代码。

44. 发明申请

US20100199238A1 Systematic Method for Variable Layout Shrink 有权
标题翻译：可变布局收缩的系统方法
公开(公告)号：US20100199238A1
公开(公告)日：2010-08-05
申请号：US12617046
申请日：2009-11-12
申请人： Fu-Chieh Hsu , Louis Chao-Chiuan Liu , Lee-Chung Lu , Yi-Kan Cheng
发明人： Fu-Chieh Hsu , Louis Chao-Chiuan Liu , Lee-Chung Lu , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values.
摘要翻译：一种用于集成电路设计的方法包括提供集成电路的布局; 确定集成电路的关键参数; 确定关键参数的目标值; 并且使用第一收缩百分比来执行布局的第一收缩以产生收缩的布局。通过从缩小布局生成关键参数的值来评估收缩布局。找到关键参数的值的一部分不能满足相应的目标值。提供用于调整缩小布局的制造过程的指南，使得关键参数的值的部分可以满足相应的目标值。

45. 发明授权

US09672315B2 Optimization for circuit migration 有权
公开(公告)号：US09672315B2
公开(公告)日：2017-06-06
申请号：US12846594
申请日：2010-07-29
申请人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu “Alex” Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
发明人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu “Alex” Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5068 , G06F17/5072
摘要： An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

46. 发明授权

US08418117B2 Chip-level ECO shrink 有权
标题翻译：芯片级ECO收缩
公开(公告)号：US08418117B2
公开(公告)日：2013-04-09
申请号：US12831982
申请日：2010-07-07
申请人： Huang-Yu Chen , Ho Che Yu , Chung-Hsing Wang , Hsiao-Shu Chao , Yi-Kan Cheng , Lee-Chung Lu
发明人： Huang-Yu Chen , Ho Che Yu , Chung-Hsing Wang , Hsiao-Shu Chao , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/0207
摘要： In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.
摘要翻译：在形成集成电路的方法中，提供包括第一知识产权（IP）的芯片表示的布局。生成与第一个IP重叠并从第一个IP边缘延伸出来的切割线。切割线将芯片表示划分成多个电路区域。多个电路区域相对于第一IP的位置向外偏移以产生空间。第一个IP被吹入空间，产生一个IP地址。然后执行直接收缩。

47. 发明授权

US08286119B2 Systematic method for variable layout shrink 有权
标题翻译：变量布局收缩的系统方法
公开(公告)号：US08286119B2
公开(公告)日：2012-10-09
申请号：US12617046
申请日：2009-11-12
申请人： Fu-Chieh Hsu , Louis Chao-Chiuan Liu , Lee-Chung Lu , Yi-Kan Cheng
发明人： Fu-Chieh Hsu , Louis Chao-Chiuan Liu , Lee-Chung Lu , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values.
摘要翻译：一种用于集成电路设计的方法包括提供集成电路的布局; 确定集成电路的关键参数; 确定关键参数的目标值; 并且使用第一收缩百分比来执行布局的第一收缩以产生收缩的布局。通过从缩小布局生成关键参数的值来评估收缩布局。找到关键参数的值的一部分不能满足相应的目标值。提供用于调整缩小布局的制造过程的指南，使得关键参数的值的部分可以满足相应的目标值。

48. 发明授权

US08245174B2 Double patterning friendly lithography method and system 有权
标题翻译：双重图案友好光刻方法和系统
公开(公告)号：US08245174B2
公开(公告)日：2012-08-14
申请号：US12549087
申请日：2009-08-27
申请人： Yi-Kan Cheng , Ru-Gun Liu , Lee-Chung Lu
发明人： Yi-Kan Cheng , Ru-Gun Liu , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC.
摘要翻译：一种方法包括接收要包括在集成电路（IC）布局中的多个单元的标识，包括要彼此连接的多个单元格内的单元对对的列表。识别出第一路由路径，以便在这些小区对内的小区之间使用一维（1-D）路由连接最大数量的小区对。从预定的二维（2-D）路由模式集合中选择第二路由路径，以连接不能通过1-D路由连接的任何一对小区。第一和第二路由路径被输出到机器可读存储介质，以由用于控制制造IC的半导体制造工艺的控制系统读取。

49. 发明申请

US20110023002A1 DOUBLE PATTERNING FRIENDLY LITHOGRAPHY METHOD AND SYSTEM 有权
标题翻译：双重图案友好的方法和系统
公开(公告)号：US20110023002A1
公开(公告)日：2011-01-27
申请号：US12549087
申请日：2009-08-27
申请人： Yi-Kan Cheng , Ru-Gun Liu , Lee-Chung Lu
发明人： Yi-Kan Cheng , Ru-Gun Liu , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC.
摘要翻译：一种方法包括接收要包括在集成电路（IC）布局中的多个单元的标识，包括要彼此连接的多个单元格内的单元对对的列表。识别出第一路由路径，以便在这些小区对内的小区之间使用一维（1-D）路由连接最大数量的小区对。从预定的二维（2-D）路由模式集合中选择第二路由路径，以连接不能通过1-D路由连接的任何一对小区。第一和第二路由路径被输出到机器可读存储介质，以由用于控制制造IC的半导体制造工艺的控制系统读取。

50. 发明申请

US20120052422A1 MASK-SHIFT-AWARE RC EXTRACTION FOR DOUBLE PATTERNING DESIGN 有权
标题翻译： MASK-SHIFT-AWARE RC提取双重图案设计
公开(公告)号：US20120052422A1
公开(公告)日：2012-03-01
申请号：US12872938
申请日：2010-08-31
申请人： Lee-Chung Lu , Yi-Kan Cheng , Hsiao-Shu Chao , Ke-Ying Su , Cheng-Hung Yeh , Dian-Hau Chen , Ru-Gun Liu , Wen-Chun Huang
发明人： Lee-Chung Lu , Yi-Kan Cheng , Hsiao-Shu Chao , Ke-Ying Su , Cheng-Hung Yeh , Dian-Hau Chen , Ru-Gun Liu , Wen-Chun Huang
IPC分类号： G03C7/20
CPC分类号： G03F1/70
摘要： A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.
摘要翻译：一种方法包括提供集成电路设计的布局，以及从布局生成多个双重图案化分解，多个双重图案化分解中的每一个包括分离到第一掩模的图案和双图案掩模组的第二掩模。确定第一和第二掩模之间的最大偏移，其中最大偏移是用于在晶片上实现布局的制造过程中的最大预期掩模移位。对于多个双重图案化分解中的每一个，使用由最大偏移限定的范围内的掩模移位来模拟最坏情况的性能值。

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