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41. 发明授权

US6100196A Method of making a copper interconnect with top barrier layer 有权
标题翻译：制造与顶部阻挡层的铜互连的方法
公开(公告)号：US6100196A
公开(公告)日：2000-08-08
申请号：US396254
申请日：1999-09-15
申请人： Lap Chan , Jia Zhen Zheng
发明人： Lap Chan , Jia Zhen Zheng
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76843 , H01L23/53238 , H01L2924/0002
摘要： A method for making copper interconnections in an integrated circuit is described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.
摘要翻译：描述了在集成电路中制造铜互连的方法。该结构是镶嵌铜连接器，其上表面与嵌入其中的绝缘层的上表面共面。通过两个阻挡层防止铜从连接器的扩散。一个位于连接器和绝缘层之间的界面处，而第二屏障是覆盖连接器的上表面的绝缘层。镶嵌工艺包括用铜填充绝缘体表面的沟槽，然后通过化学去除多余的沟槽。抛光。由于光致抗蚀剂从不与铜直接接触，因此已经有效地消除了抗蚀剂灰化期间铜氧化的问题。

42. 发明授权

US5728621A Method for shallow trench isolation 失效
标题翻译：浅沟槽隔离方法
公开(公告)号：US5728621A
公开(公告)日：1998-03-17
申请号：US845870
申请日：1997-04-28
申请人： Jia Zhen Zheng , Charlie Wee Song Tay , Wei Lu , Lap Chan
发明人： Jia Zhen Zheng , Charlie Wee Song Tay , Wei Lu , Lap Chan
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A new method for forming planarized high quality oxide shallow trench isolation is described. A nitride layer overlying a pad oxide layer is provided over the surface of a semiconductor substrate. A plurality of isolation trenches is etched through the nitride and pad oxide layers into the semiconductor substrate wherein there is at least one first wide nitride region between two of the isolation trenches and at least one second narrow nitride region between another two of the isolation trenches. A high density plasma (HDP) oxide layer is deposited over the nitride layer filling the isolation trenches wherein the HDP oxide deposits more thickly in the first region over the wide nitride layer and deposits more thinly in the second region over the narrow nitride layer and wherein the difference in step heights of the HDP oxide between the first region and a region overlying an isolation trench is a first height. A layer of spin-on-glass is coated over the HDP oxide layer wherein the difference in step heights of the spin-on-glass material between the first region and the region overlying an isolation trench is a second height smaller than the first height. The spin-on-glass layer and portions of the HDP oxide layer in the first region are etched away. The spin-on-glass layer and HDP oxide layer remaining are polished away wherein the substrate is planarized.
摘要翻译：描述了形成平面化高质量氧化物浅沟槽隔离的新方法。覆盖衬垫氧化物层的氮化物层设置在半导体衬底的表面上。通过氮化物和衬垫氧化物层蚀刻多个隔离沟槽到半导体衬底中，其中在两个隔离沟槽之间存在至少一个第一宽氮化物区域和在另外两个隔离沟槽之间的至少一个第二窄氮化物区域。在填充隔离沟槽的氮化物层上沉积高密度等离子体（HDP）氧化物层，其中HDP氧化物在宽氮化物层上的第一区域中更厚地沉积，并且在第二区域上更薄地沉积在窄氮化物层上，并且其中在第一区域和覆盖隔离沟槽的区域之间的HDP氧化物的阶跃高度的差异是第一高度。在HDP氧化物层上涂覆一层旋涂玻璃，其中在第一区域和覆盖隔离沟槽的区域之间的旋涂玻璃材料的阶梯高度的差异是比第一高度小的第二高度。旋转玻璃层和第一区域中的HDP氧化物层的部分被蚀刻掉。抛光剩余的旋涂玻璃层和HDP氧化物层，其中衬底被平坦化。

43. 发明授权

US06747314B2 Method to form a self-aligned CMOS inverter using vertical device integration 失效
标题翻译：使用垂直器件集成形成自对准CMOS反相器的方法
公开(公告)号：US06747314B2
公开(公告)日：2004-06-08
申请号：US10242483
申请日：2002-09-12
申请人： Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy , Jia Zhen Zheng , Lap Chan , Elgin Quek
发明人： Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy , Jia Zhen Zheng , Lap Chan , Elgin Quek
IPC分类号： H01L2976
CPC分类号： H01L21/84 , H01L21/823885 , H01L27/1203
摘要： A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprise silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS and PMOS channel regions and lining the gate trench. A polysilicon layer is deposited and etched back to form polysilicon sidewalls and to thereby form gates for the closely-spaced, vertical NMOS and PMOS transistor pair.
摘要翻译：实现了在集成电路器件中形成紧密间隔的垂直NMOS和PMOS晶体管对的方法。衬底包括硅注入氧化物（SIMOX），其中氧化物层夹在下层和上层的硅层之间。离子选择性地注入到上覆硅层的第一部分中以形成用于NMOS晶体管的漏极，沟道区和源极。漏极直接形成在氧化层的上方，沟道区形成在漏极上方，源极形成在沟道区域的上方。离子选择性地注入到上层硅层的第二部分中以形成用于PMOS晶体管的漏极，沟道区和源极。漏极直接形成在氧化层的上方，PMOS沟道区形成在漏极上方，源极形成在沟道区域的上方。 PMOS晶体管漏极与所述NMOS晶体管漏极接触。通过NMOS和PMOS源极和沟道区域蚀刻栅极沟槽。栅极沟槽在NMOS和PMOS漏极处终止并暴露NMOS和PMOS沟道区的侧壁。形成栅极氧化层，覆盖NMOS沟道区和PMOS沟道区，并衬在栅极沟槽。沉积多晶硅层并回蚀刻以形成多晶硅侧壁，从而形成用于紧密间隔的垂直NMOS和PMOS晶体管对的栅极。

44. 发明授权

US06417056B1 Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge 失效
标题翻译：通过在栅极边缘形成微动开关来形成低重叠电容晶体管的方法
公开(公告)号：US06417056B1
公开(公告)日：2002-07-09
申请号：US09981439
申请日：2001-10-18
申请人： Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan
发明人： Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan
IPC分类号： H01L21336
CPC分类号： H01L29/66636 , H01L29/0649 , H01L29/665 , H01L29/66545 , H01L29/7834
摘要： A method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant is described. A gate electrode is provided overlying a gate dielectric layer on a substrate and having a hard mask layer thereover. An oxide layer is formed overlying the substrate. First spacers are formed on sidewalls of the gate electrode and overlying the oxide layer. Source/drain extensions are implanted. Second spacers are formed on the first spacers. Source/drain regions are implanted. A dielectric layer is deposited overlying the gate electrode and the oxide layer and planarized to the hard mask layer whereby the first and second spacers are exposed. The exposed second spacers and underlying oxide layer are removed. The exposed substrate underlying the second spacers is etched into to form a microtrench undercutting the gate oxide layer at an edge of the gate electrode. The microtrench is filled with an epitaxial oxide layer and planarized to the hard mask layer. The dielectric layer is patterned to form third spacers on the epitaxial oxide layer. The microtrench reduces the effective dielectric constant at the overlap between the gate and the source/drain extensions to complete formation of a transistor having low overlap capacitance.
摘要翻译：描述了通过在栅极边缘处形成微通孔以形成具有低重叠电容的晶体管以降低有效介电常数的方法。栅电极被设置在衬底上的栅介电层上，并且在其上具有硬掩模层。在衬底上形成氧化物层。第一间隔物形成在栅电极的侧壁上并覆盖氧化物层。源/漏扩展被植入。第二间隔件形成在第一间隔件上。源极/漏极区域被植入。沉积覆盖在栅电极和氧化物层上的介电层，并且平坦化到硬掩模层，由此使第一和第二间隔物暴露。去除暴露的第二间隔物和下面的氧化物层。蚀刻第二间隔物下面的暴露的基底以形成在栅电极的边缘处切割栅极氧化物层的微切口。微通孔填充有外延氧化物层并且平坦化到硬掩模层。图案化电介质层以在外延氧化物层上形成第三间隔物。微通道减小栅极和源极/漏极延伸部之间的重叠处的有效介电常数，以完成具有低重叠电容的晶体管的形成。

45. 发明授权

US06406945B1 Method for forming a transistor gate dielectric with high-K and low-K regions 有权
标题翻译：用于形成具有高K和低K区的晶体管栅极电介质的方法
公开(公告)号：US06406945B1
公开(公告)日：2002-06-18
申请号：US09769810
申请日：2001-01-26
申请人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
发明人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
IPC分类号： H01L21335
CPC分类号： H01L29/517 , H01L21/28167 , H01L21/28194 , H01L29/42376 , H01L29/512 , H01L29/518 , H01L29/66583 , Y10S257/90
摘要： A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the spacers. The spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.
摘要翻译：一种形成具有不同介电常数区域的栅极电介质的方法。在半导体结构上形成虚拟电介质层。图案化虚拟介质层以形成栅极开口。在虚拟电介质上和栅极开口中形成高K电介质层。在高K电介质层上形成低K电介质层。在栅极开口边缘的低K电介质层上形成间隔物。低K电介质层从间隔物之间的栅极开口的底部去除。移除间隔件以形成阶梯式门开口。阶梯式门开口在侧壁和栅极开口底部的边缘处具有高K电介质层和低K电介质层，并且仅在台阶底部中心的高k电介质层开门在阶梯式门开口形成栅电极。

46. 发明授权

US06188135B1 Copper interconnect with top barrier layer 有权
标题翻译：铜互连与顶部阻挡层
公开(公告)号：US06188135B1
公开(公告)日：2001-02-13
申请号：US09294047
申请日：1999-04-19
申请人： Lap Chan , Jia Zhen Zheng
发明人： Lap Chan , Jia Zhen Zheng
IPC分类号： H01L2348
CPC分类号： H01L21/76834 , H01L21/76843 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.
摘要翻译：描述了在集成电路中制造铜互连的结构和方法。该结构是镶嵌铜连接器，其上表面与嵌入其中的绝缘层的上表面共面。通过两个阻挡层防止铜从连接器的扩散。一个位于连接器和绝缘层之间的界面处，而第二屏障是覆盖连接器的上表面的绝缘层。镶嵌工艺包括用铜填充绝缘体表面的沟槽，然后通过化学去除多余的沟槽。抛光。由于光致抗蚀剂从不与铜直接接触，因此已经有效地消除了抗蚀剂灰化期间铜氧化的问题。

47. 发明授权

US6069069A Method for planarizing a low dielectric constant spin-on polymer using nitride etch stop 失效
标题翻译：使用氮化蚀刻停止平面化低介电常数旋涂聚合物的方法
公开(公告)号：US6069069A
公开(公告)日：2000-05-30
申请号：US767009
申请日：1996-12-16
申请人： Simon Yew-Meng Chooi , Jia Zhen Zheng , Lap Chan
发明人： Simon Yew-Meng Chooi , Jia Zhen Zheng , Lap Chan
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/314 , H01L21/316 , H01L21/4763
CPC分类号： H01L21/31053 , H01L21/31055 , H01L21/3124 , H01L21/3145 , H01L21/316
摘要： A method for preserving the integrity of the underlying metal lines during planarization by inserting a nitride layer as an etch stop in an oxide-nitride-oxide dielectric layer underlying a spin-on polymer is described. Semiconductor device structures are provided in and on a semiconductor substrate. A conducting layer is deposited overlying the surfaces of the semiconductor device structures and patterned to form conducting lines wherein a gap is formed between the conducting lines. A first dielectric layer is deposited over the surfaces of the conducting lines wherein the first dielectric layer contains an etch stop layer wherein the gap remains between the conducting lines. A second dielectric layer is deposited overlying the first dielectric layer wherein the gap is filled by the second dielectric layer. The second dielectric layer is etched back so that the second dielectric layer remains only within the gap wherein the etch stop layer preserves the integrity of the underlying conducting lines. A third dielectric layer is deposited over the first and second dielectric layers and planarized. Alternatively, instead of etching back the second dielectric layer, chemical mechanical polishing (CMP) is used to planarize the layer wherein the etch stop acts as a CMP stop. A third dielectric layer is then deposited over the substrate to complete fabrication of the integrated circuit device.
摘要翻译：描述了在平面化期间通过将氮化物层作为蚀刻停留点插入在旋涂聚合物下面的氧化物 - 氮化物 - 氧化物介电层中来保持底层金属线的完整性的方法。半导体器件结构设置在半导体衬底中和半导体衬底上。导电层沉积在半导体器件结构的表面上，并被图案化以形成导线，其中在导线之间形成间隙。第一电介质层沉积在导电线的表面上，其中第一介电层包含蚀刻停止层，其中间隙保留在导线之间。沉积第二介电层，覆盖第一介电层，其中间隙由第二介电层填充。第二介电层被回蚀刻，使得第二电介质层仅保留在间隙内，其中蚀刻停止层保持下面的导电线的完整性。第三电介质层沉积在第一和第二电介质层上并且被平坦化。或者，代替蚀刻回第二介电层，化学机械抛光（CMP）用于平坦化该层，其中蚀刻停止作为CMP停止。然后将第三介电层沉积在衬底上以完成集成电路器件的制造。

48. 发明申请

US20050196931A1 Self-aligned lateral heterojunction bipolar transistor 有权
标题翻译：自对准横向异质结双极晶体管
公开(公告)号：US20050196931A1
公开(公告)日：2005-09-08
申请号：US11123748
申请日：2005-05-04
申请人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-fu Chu
发明人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-fu Chu
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/737
摘要： A lateral heterojunction bipolar transistor (HBT), comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

49. 发明申请

US20050145953A1 Heterojunction BiCMOS integrated circuits and method therefor 审中-公开
标题翻译：异质结BiCMOS集成电路及其方法
公开(公告)号：US20050145953A1
公开(公告)日：2005-07-07
申请号：US10752454
申请日：2004-01-05
申请人： Lap Chan , Jia Zheng , Purakh Verma , Jian Li , Shao-fu Chu
发明人： Lap Chan , Jia Zheng , Purakh Verma , Jian Li , Shao-fu Chu
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L31/113
CPC分类号： H01L29/66242 , H01L21/8249 , H01L27/0623
摘要： A method of manufacturing a BiCMOS integrated circuit including a CMOS transistor having a gate structure, and a heterojunction bipolar transistor having an extrinsic base structure. A substrate is provided, and a polysilicon layer is formed over the substrate. The gate structure and the extrinsic base structure are formed in the polysilicon layer. A plurality of contacts is formed through the interlevel dielectric layer to the CMOS transistor and the heterojunction bipolar transistor.
摘要翻译：一种制造包括具有栅极结构的CMOS晶体管的BiCMOS集成电路的方法和具有外在基极结构的异质结双极晶体管。提供衬底，并且在衬底上形成多晶硅层。栅极结构和非本征基极结构形成在多晶硅层中。多个触点通过层间介质层形成到CMOS晶体管和异质结双极晶体管。

50. 发明申请

US20050101096A1 SELF-ALIGNED LATERAL HETEROJUNCTION BIPOLAR TRANSISTOR 有权
标题翻译：自对准侧向异相双极晶体管
公开(公告)号：US20050101096A1
公开(公告)日：2005-05-12
申请号：US10703284
申请日：2003-11-06
申请人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-Fu Chu
发明人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-Fu Chu
IPC分类号： H01L21/331 , H01L29/737 , H01L21/8222
CPC分类号： H01L29/66242 , H01L29/737
摘要： A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：提供一种用于制造横向异质结双极晶体管（HBT）的方法，包括半导体衬底上的第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

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