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41. 发明授权

US5976945A Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor 失效
标题翻译：在包含二维沟槽电容器的SOI晶片上制造DRAM单元结构的方法
公开(公告)号：US5976945A
公开(公告)日：1999-11-02
申请号：US974452
申请日：1997-11-20
申请人： Min-Hwa Chi , Chih-Yuan Lu
发明人： Min-Hwa Chi , Chih-Yuan Lu
IPC分类号： H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/12 , H01L21/20
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/10832 , H01L27/1203
摘要： A method for fabricating a DRAM cell, on a SOI layer, is described, featuring the incorporation of a two dimensional, trench capacitor structure, for increased DRAM cell signal, and the use of a polysilicon storage node structure to connect the SOI layer to the semiconductor substrate, to eliminate a floating body effect. A two dimensional trench is created by initially forming a vertical trench, through the SOI layer, through the underlying insulator layer, and into the semiconductor substrate. An isotropic etch is than performed to laterally remove a specific amount of insulator layer, exposed in the vertical trench, creating the lateral component of the two dimensional trench. A deposited polysilicon layer, coating the sides of the two dimensional trench, is used as the storage node structure, for the two dimensional, trench capacitor structure, while also connecting the SOI layer to the semiconductor substrate.
摘要翻译：描述了在SOI层上制造DRAM单元的方法，其特征在于结合用于增加的DRAM单元信号的二维沟槽电容器结构，以及使用多晶硅存储节点结构将SOI层连接到半导体衬底，消除浮体效应。通过初始形成穿过SOI层的垂直沟槽，穿过下面的绝缘体层并进入半导体衬底而形成二维沟槽。进行各向同性蚀刻以横向移除在垂直沟槽中暴露的特定量的绝缘体层，产生二维沟槽的横向分量。作为二维沟槽电容器结构的存储节点结构，同时也将SOI层与半导体基板连接，使用涂覆二维沟槽的侧面的沉积多晶硅层。

42. 发明授权

US5843820A Method of fabricating a new dynamic random access memory (DRAM) cell having a buried horizontal trench capacitor 失效
标题翻译：制造具有埋置水平沟槽电容器的新的动态随机存取存储器（DRAM）单元的方法
公开(公告)号：US5843820A
公开(公告)日：1998-12-01
申请号：US939971
申请日：1997-09-29
申请人： Chih-Yuan Lu
发明人： Chih-Yuan Lu
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10832
摘要： An improved dynamic random access memory (DRAM) cell using a novel buried horizontal trench capacitor was achieved. A capacitor trench is etched in a silicon substrate. A first high-k dielectric layer is formed on the trench surface, and the trench is filled with a first polysilicon layer and polished back. A second high-k dielectric is deposited and patterned over the polySi-filled trench. A P.sup.- epitaxy is grown on the substrate that also grows inward over the trench, while an amorphous silicon layer of decreasing top surface area grows on the dielectric over the trench. A field oxide is formed in the epi surrounding and isolating a device area aligned over the trench capacitor. A node contact hole is etched in the epi/amorphous Si to the capacitor and has an oxide liner on the sidewall. A second polySi is deposited and etched back to form the node contact to the buried trench capacitor. The gate electrode (access transistor) is formed on the epi layer over the capacitor, and adjacent to the node contact which is connected to one of the two FET source/drain (S/D) areas, while the second S/D is connected to a bit line. The surface over the cell, free for the bit line, and the FET over the capacitor reduces the cell size, while the buried horizontal trench capacitor increases capacitance.
摘要翻译：实现了使用新颖的埋地水平沟槽电容器的改进的动态随机存取存储器（DRAM）单元。在硅衬底中蚀刻电容器沟槽。在沟槽表面上形成第一高k电介质层，并且沟槽填充有第一多晶硅层并抛光。在多晶硅填充的沟槽上沉积和图案化第二高k电介质。在衬底上生长P-外延，其也在沟槽上向内生长，而在沟槽上的电介质上生长的顶表面积减小的非晶硅层增长。在外围形成场氧化物，并且隔离沟槽电容器对准的器件区域。节点接触孔在外延/非晶Si中蚀刻到电容器，并且在侧壁上具有氧化物衬垫。沉积并蚀刻第二多晶硅以形成与埋沟电容器的节点接触。栅电极（存取晶体管）形成在电容器上的外延层上，并且与连接到两个FET源/漏（S / D）区中的一个的节点接触相邻，而第二S / D连接到一点点电池上的表面，位线自由，电容器上的FET降低了电池尺寸，而埋置的水平沟槽电容器增加了电容。

43. 发明授权

US5519238A Rippled polysilicon surface capacitor electrode plate for high density dram 失效
标题翻译：波纹多晶硅表面电容器电极板用于高密度电极
公开(公告)号：US5519238A
公开(公告)日：1996-05-21
申请号：US13937
申请日：1993-02-05
申请人： Chih-Yuan Lu
发明人： Chih-Yuan Lu
IPC分类号： H01L21/02 , H01L21/3213 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： H01L21/32139 , H01L28/92 , Y10S148/104 , Y10S438/948 , Y10S438/964
摘要： A new method to produce a microminiturized capacitor having a regular microscopic ripple surface electrode is achieved by depositing a first polysilicon layer over a suitable insulating base. A resist layer is formed over the first polysilicon layer. The resist layer is exposed through a mask having a pattern of regular spaced openings in the areas of the planned capacitor to radiant energy in sufficient quantity to under expose, out of focus expose or a combination of under expose and out of focus expose the resist layer. The mask is shifted a fixed and short distance. The resist layer is exposed through the shifted mask to radiant energy in sufficient quantity to under expose or out of focus expose, or a combination of under expose or out of focus expose the resist layer again and in a different location. The shifting of the mask and exposing resist steps are repeated until a pattern of the regular microscopic ripple has been formed in the resist layer. The resist layer is developed to leave the pattern of regular microscopic ripple in the surface of the resist layer. The resist layer and said first polysilicon layer is uniformly and anisotropically etched to create the pattern of regular microscopic ripple in the surface of the first polysilicon layer. The remaining resist layer is removed. An insulating layer is deposited over the ripple surface. The capacitor structure is completed by depositing a second polysilicon layer over the insulating layer.
摘要翻译：通过在合适的绝缘基底上沉积第一多晶硅层来实现产生具有规则微观波纹表面电极的微量化电容器的新方法。在第一多晶硅层上形成抗蚀剂层。抗蚀剂层通过具有在计划电容器的区域中具有规则间隔的开口的图案的掩模暴露于足够数量的辐射能以暴露下来，脱离曝光或曝光和失焦之外的组合暴露抗蚀剂层。面罩移动一个固定和短距离。抗蚀剂层通过移动的掩模曝光到足够数量的辐射能以暴露或脱离焦点暴露，或暴露或失焦的组合再次暴露在不同的位置。重复掩模移动和曝光抗蚀剂步骤，直到在抗蚀剂层中形成规则的微细波纹图案。抗蚀剂层被开发以在抗蚀剂层的表面中留下规则的微观纹理图案。均匀且各向异性地蚀刻抗蚀剂层和所述第一多晶硅层，以在第一多晶硅层的表面产生规则的微观纹理图案。去除剩余的抗蚀剂层。绝缘层沉积在波纹表面上。通过在绝缘层上沉积第二多晶硅层来完成电容器结构。

44. 发明授权

US5451537A Method of forming a DRAM stack capacitor with ladder storage node 失效
标题翻译：用梯形存储节点形成DRAM堆叠电容器的方法
公开(公告)号：US5451537A
公开(公告)日：1995-09-19
申请号：US289633
申请日：1994-08-12
申请人： Horng-Huei Tseng , Chih-Yuan Lu
发明人： Horng-Huei Tseng , Chih-Yuan Lu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10808 , H01L28/82 , H01L28/86
摘要： A method, and resultant structure, is described for fabricating a DRAM (Dynamic Random Access Memory) cell having a stack capacitor with a ladder storage node, connected to a MOS (Metal Oxide Semiconductor) transistor with source and drain regions, to form a DRAM cell. A bottom electrode is connected to and extends up from the source region of the transistor, and has a top surface with a central cavity, and side surfaces extending down from the top surface in a step-like manner. These step-like sides are formed by a repeated two-step process of removing a portion of the vertical walls of a photoresist mask and removing a portion of the top surface of a layer of polysilicon from which the bottom electrode is formed. There is a capacitor dielectric over the bottom electrode. A top electrode is formed over the capacitor dielectric.
摘要翻译：描述了一种用于制造具有梯形存储节点的堆叠电容器的DRAM（动态随机存取存储器）单元，其连接到具有源极和漏极区域的MOS（金属氧化物半导体）晶体管，以形成DRAM 细胞。底部电极连接到晶体管的源极区域并且从晶体管的源极区域向上延伸，并具有具有中心空腔的顶表面，并且侧表面以阶梯状方式从顶表面向下延伸。通过重复的两步法除去光致抗蚀剂掩模的垂直壁的一部分并且去除形成底部电极的多晶硅层的顶表面的一部分，形成这些阶梯状侧。底部电极上有一个电容电介质。在电容器电介质上形成顶部电极。

45. 发明授权

US5396093A Vertical DRAM cross point memory cell and fabrication method 失效
标题翻译：垂直DRAM交叉点存储单元及制造方法
公开(公告)号：US5396093A
公开(公告)日：1995-03-07
申请号：US289741
申请日：1994-08-12
申请人： Chih-Yuan Lu
发明人： Chih-Yuan Lu
IPC分类号： H01L21/8242 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10876
摘要： A method is described for making a vertical DRAM cell which includes a vertical channel field effect transistor having a gate electrode and source/drain elements and a capacitor. A pattern of field oxide isolation in a silicon substrate is provided wherein there are a pattern of openings to the silicon substrate. A pattern is formed of buried bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and buried bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes so that it covers the gate dielectric. The doped polysilicon layer is patterned and etched to form the gate electrode and word lines which are perpendicular to the pattern of buried bit lines. The source/drain elements are formed surrounding the gate electrode in the surface of the substrate by ion implantation using the field oxide and gate electrode and word lines as the mask. The buried bit lines form common and additional source/drain elements. An insulating layer is provided over the pattern of field oxide insulation, word lines and openings to the source/drain elements surrounding the gate electrode. An opening is formed through the insulating layer surrounding the gate electrode. A capacitor is formed in and over the opening through the insulating layer.
摘要翻译：描述了一种用于制造垂直DRAM单元的方法，该垂直DRAM单元包括具有栅电极和源/漏元件和电容器的垂直沟道场效应晶体管。提供了硅衬底中的场氧化物隔离的图案，其中存在到硅衬底的开口图案。掩模位线形成图案，并且具有位于每个开口内的孔的孔的线图案，所述硅衬底的哪些孔和掩埋位线彼此垂直，并且线在计划位置处交叉垂直DRAM单元以与硅衬底的开口图案相同。在孔的表面上形成栅极电介质。在孔内和上方形成掺杂多晶硅层，使其覆盖栅极电介质。对掺杂多晶硅层进行图案化和蚀刻以形成垂直于掩埋位线图案的栅电极和字线。源极/漏极元件通过使用场氧化物和栅电极以及字线作为掩模的离子注入形成在衬底的表面中的栅电极周围。埋置的位线形成公共和附加的源极/漏极元件。在栅极电极周围的源极/漏极元件的场氧化物绝缘，字线和开口的图案上设置绝缘层。通过围绕栅电极的绝缘层形成开口。通过绝缘层在开口内和上方形成电容器。

46. 发明授权

US5362665A Method of making vertical DRAM cross point memory cell 失效
标题翻译：制作垂直DRAM交叉点存储单元的方法
公开(公告)号：US5362665A
公开(公告)日：1994-11-08
申请号：US194736
申请日：1994-02-14
申请人： Chih-Yuan Lu
发明人： Chih-Yuan Lu
IPC分类号： H01L21/8242 , H01L21/70
CPC分类号： H01L27/10876
摘要： A pattern of field oxide isolation in a silicon substrate is provided wherein there are a pattern of openings to the silicon substrate. A pattern is formed of buried bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and buried bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes. The doped polysilicon layer is etched to form the gate electrode and word lines which are perpendicular to the pattern of buried bit lines. The source/drain elements are formed surrounding the gate electrode in the surface of the substrate by ion implantation using the field oxide and gate electrode and word lines as the mask. The buried bit lines form common and additional source/drain elements. An insulating layer is provided over the pattern of field oxide insulation, word lines and openings to the source/drain elements surrounding the gate electrode. An opening is formed through the insulating layer surrounding the gate electrode. A capacitor is formed in and over the opening through the insulating layer.
摘要翻译：提供了硅衬底中的场氧化物隔离的图案，其中存在到硅衬底的开口图案。掩模位线形成图案，并且具有位于每个开口内的孔的孔的线图案，所述硅衬底的哪些孔和掩埋位线彼此垂直，并且线在计划位置处交叉垂直DRAM单元以与硅衬底的开口图案相同。在孔的表面上形成栅极电介质。在孔内和上方形成掺杂多晶硅层。蚀刻掺杂多晶硅层以形成垂直于掩埋位线图案的栅电极和字线。源极/漏极元件通过使用场氧化物和栅电极以及字线作为掩模的离子注入形成在衬底的表面中的栅电极周围。埋置的位线形成公共和附加的源极/漏极元件。在栅极电极周围的源极/漏极元件的场氧化物绝缘，字线和开口的图案上设置绝缘层。通过围绕栅电极的绝缘层形成开口。通过绝缘层在开口内和上方形成电容器。

47. 发明授权

US07236394B2 Transistor-free random access memory 有权
标题翻译：无晶体管随机存取存储器
公开(公告)号：US07236394B2
公开(公告)日：2007-06-26
申请号：US10464938
申请日：2003-06-18
申请人： Yi Chou Chen , Wen-Jer Tsai , Chih-Yuan Lu
发明人： Yi Chou Chen , Wen-Jer Tsai , Chih-Yuan Lu
IPC分类号： G11C11/34
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2213/77
摘要： A memory core includes a bit line and a word line. The memory core also includes a core cell in electrical communication with the word line and the bit line. The core cell includes a threshold changing material. The threshold changing material is programmed to enable access to the core cell based upon a voltage applied to the word line. Methods for accessing a memory core cell also are described.
摘要翻译：存储器核心包括位线和字线。存储器核心还包括与字线和位线电通信的核心单元。核心单元包括阈值变化材料。阈值改变材料被编程为使得能够基于施加到字线的电压来访问核心单元。还描述了访问存储器核心单元的方法。

48. 发明授权

US06218693B1 Dynamic random access memory (DRAM) cell having a buried horizontal trench capacitor by a novel fabrication method 有权
标题翻译：通过新颖的制造方法具有埋入水平沟槽电容器的动态随机存取存储器（DRAM）单元
公开(公告)号：US06218693B1
公开(公告)日：2001-04-17
申请号：US09163384
申请日：1998-09-30
申请人： Chih-Yuan Lu
发明人： Chih-Yuan Lu
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10832
摘要： An improved dynamic random access memory (DRAM) cell using a novel buried horizontal trench capacitor was achieved. A capacitor trench is etched in a silicon substrate. A first high-k dielectric layer is formed on the trench surface, and the trench is filled with a first polysilicon layer and polished back. A second high-k dielectric is deposited and patterned over the polySi-filled trench. A P− epitaxy is grown on the substrate that also grows inward over the trench, while an amorphous silicon layer of decreasing top surface area grows on the dielectric over the trench. A field oxide is formed in the epi surrounding and isolating a device area aligned over the trench capacitor. A node contact hole is etched in the epi/amorphous Si to the capacitor and has an oxide liner on the sidewall. A second polySi is deposited and etched back to form the node contact to the buried trench capacitor. The gate electrode (access transistor) is formed on the epi layer over the capacitor, and adjacent to the node contact which is connected to one of the two FET source/drain (S/D) areas, while the second S/D is connected to a bit line. The surface over the cell, free for the bit line, and the FET over the capacitor reduces the cell size, while the buried horizontal trench capacitor increases capacitance.
摘要翻译：实现了使用新颖的埋地水平沟槽电容器的改进的动态随机存取存储器（DRAM）单元。在硅衬底中蚀刻电容器沟槽。在沟槽表面上形成第一高k电介质层，并且沟槽填充有第一多晶硅层并抛光。在多晶硅填充的沟槽上沉积和图案化第二高k电介质。在衬底上生长P-外延，其也在沟槽上向内生长，而在沟槽上的电介质上生长的顶表面积减小的非晶硅层增长。在外围形成场氧化物，并且隔离沟槽电容器对准的器件区域。节点接触孔在外延/非晶Si中蚀刻到电容器，并且在侧壁上具有氧化物衬垫。沉积并蚀刻第二多晶硅以形成与埋沟电容器的节点接触。栅电极（存取晶体管）形成在电容器上的外延层上，并且与连接到两个FET源/漏（S / D）区中的一个的节点接触相邻，而第二S / D连接到一点点电池上的表面，位线自由，电容器上的FET降低了电池尺寸，而埋置的水平沟槽电容器增加了电容。

49. 发明授权

US5930661A Substrate clamp design for minimizing substrate to clamp sticking during thermal processing of thermally flowable layers 失效
标题翻译：基板夹具设计，用于最大限度地减少热可流层的热处理过程中的基板以贴紧
公开(公告)号：US5930661A
公开(公告)日：1999-07-27
申请号：US732580
申请日：1996-10-15
申请人： Chih-Yuan Lu
发明人： Chih-Yuan Lu
IPC分类号： C23C16/44 , C23C16/458 , H01L21/687 , H01L21/20 , C23C16/00 , H01L21/31 , H01L21/469
CPC分类号： H01L21/68721 , C23C16/4401 , C23C16/4585 , H01L21/68735 , H01L21/68757
摘要： A clamp for fixturing a substrate when forming and thermal processing upon the substrate a thermally flowable layer. The clamp is formed from a backing member connected to a top member through a mechanical means. The backing member and the top member are sized such that a substrate may be clamped between the backing member and the top member. A portion of the top member overlaps the substrate and leaves exposed a first portion of the substrate when the substrate is clamped between the backing member and the top member. The top member has a cross-sectional profile such that a thermally flowable layer residue formed upon the top member when a thermally flowable layer is formed upon the substrate will not flow from the top member and bridge to the thermally flowable layer when the thermally flowable layer is thermally processed.
摘要翻译：一种用于在基底上形成热处理并热处理热可流动层时固定基板的夹具。夹具由通过机械装置连接到顶部构件的背衬构件形成。所述背衬构件和所述顶部构件的尺寸设计成使得衬底可被夹持在所述衬垫构件和所述顶部构件之间。顶部构件的一部分与衬底重叠，并且当衬底夹持在衬垫构件和顶部构件之间时，露出衬底的第一部分。顶部构件具有横截面轮廓，使得当在基底上形成热可流动层时形成在顶部构件上的可热流动的层残留物将不会从顶部构件流动并桥接到热可流动层，当热可流动层被热处理。

50. 发明授权

US5827394A Step and repeat exposure method for loosening integrated circuit dice from a radiation sensitive adhesive tape backing 失效
标题翻译：从辐射敏感胶带背面松开集成电路骰子的步骤和重复曝光方法
公开(公告)号：US5827394A
公开(公告)日：1998-10-27
申请号：US999614
申请日：1997-09-25
申请人： Chih-Yuan Lu
发明人： Chih-Yuan Lu
IPC分类号： B32B38/10 , H01L21/68 , B32B35/00
CPC分类号： B32B38/10 , H01L21/6835 , H01L21/6836 , B32B2310/0831 , H01L2221/68322 , H01L2221/68327 , H01L2224/75 , H01L2224/7999 , H01L2224/98 , H01L2924/1305 , Y10S156/922 , Y10T156/11 , Y10T156/19 , Y10T29/49819 , Y10T29/49822
摘要： A method and apparatus through which there may be delaminated, within the context of a pick-and-place processing method, an integrated circuit die from an adhesive tape backing. To practice the method of the present invention, there is first provided upon an adhesive tape backing an integrated circuit die. The adhesive tape backing comprises a carrier layer and an adhesive layer formed over the carrier layer, where the adhesive layer is positioned between the integrated circuit die and the carrier layer. The adhesive layer has a first portion of the adhesive layer upon which is positioned the integrated circuit die. The adhesive character of the first portion of the adhesive layer is susceptible to substantially complete degradation through exposure to a dose of radiation. There is then exposed selectively the first portion of the adhesive layer to the dose of radiation, preferably ultra-violet (UV) radiation. Finally, the integrated circuit die is removed from the adhesive tape backing. The invention also contemplates an apparatus through which the method of the present invention may be practiced and an ultra-violet (UV) sensitive adhesive tape backing which may be employed within the method and apparatus of the invention.
摘要翻译：在拾取和放置处理方法的上下文中，可以从胶带背衬中分离出集成电路模具的方法和装置。为了实施本发明的方法，首先在胶带背面提供集成电路管芯。胶带背衬包括载体层和形成在载体层上的粘合剂层，其中粘合剂层位于集成电路管芯和载体层之间。粘合剂层具有其上定位有集成电路管芯的粘合剂层的第一部分。粘合剂层的第一部分的粘合特性易于暴露于一定剂量的辐射而基本上完全降解。然后选择性地将粘合剂层的第一部分暴露于辐射剂量，优选紫外线（UV）辐射。最后，将集成电路芯片从胶带背衬上取下。本发明还考虑了可以在本发明的方法和装置中实施本发明的方法的装置和可以采用的紫外（UV）敏感的胶带背衬。

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